Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power (original) (raw)
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Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications
Electronics
Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...
DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.
A CMOS charge pump for low voltage operation
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000
This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2V, 1.5V, 1.2V and 0.9V an output voltage of I1.5V, 8.4V, 6.5V and 4V can be generated respectively, using five pumping stages.
Charge Pump Circuits for Low-voltage Applications
VLSI Design, 2002
In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.
Power efficient charge pump in deep submicron standard cmos technology
IEEE Journal of Solid-State Circuits, 2003
A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz.
Design and Analysis of Low Power CMOS Charge Pump Circuits For Phase-Locked Loop
2015
A new high efficiency charge pump circuit is designed and realized in 130nm CMOS process. This paper work analyses the design of various CMOS Charge pumps. The performance of charge pumps mainly depends on the ability to efficiently generate high output voltages from the low input supply voltage. The shoot through current and the switching noise are being reduced by the proposed CMOS charge pump circuit. It is also used to improve the large driving capability and for eliminating the reversion loss. The proposed cross coupled charge pump has provided up to 8% percentage efficiency as compared with the conventional CMOS charge pump. The CMOS charge pump (CP) is an integral part in the phase-locked loops. CMOS charge pump circuits used for generating a high voltage from a low supply voltage are used in ICs, such as flash memories, smart power, dynamic random access memories (DRAMs), LEDs and LCD drivers(7). A charge pump is used in DRAMs to generate word-line voltage higher than the su...
Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage
Radioengineering, 2016
In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulkdriven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 µA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.
A low-voltage charge pump with wide current driving capability
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010
A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage VDD, and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process.
Journal of Semiconductors, 2010
This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-m CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm 2 ; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.
Energy harvesting applications for Low Voltage Dynamic CTS CMOS Charge Pump
This paper brings a detailed analysis and comparison of several charge pumps topologies that have not been optimized yet in order to make a relevant comparison of main parameters. The charge pumps were designed in a standard 90nm CMOS technology. Highly efficient CMOS charge pump which is designed using charge transfer switches. The circuit provides higher output voltage then existing ones. This is achieved by replacing diode with charge transfer block at the last stage of dynamic CTS charge pump. This eliminates threshold voltage loss, leakage current, and body effect problem. The charge pump are designed in a standard CMOS technology which Provides the superior pumping efficiency, settling time, ON-chip power management and voltage gain. The proposed circuit is designed and simulated using T-spice and H-spice with CMOS technology parameters.