Electrical design of a low cost and high performance plastic ball grid array package-NuBGA (original) (raw)
Related papers
A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package
IEEE Transactions on Components and Packaging Technologies, 2001
A previously validated detailed model of a 119-pin flip-chip plastic ball grid array (FC-PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, two compact models were derived, a two-resistor model (created using the JEDEC-standard based computational approach), and a multiresistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multiresistor model provided the same predictive estimates (within 5%) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks.
Temperature Cycling of Coreless Ball Grid Arrays
There are countless challenges in making mobile electronics more reliable, including the thin form factor of cellphones and tablets that is forcing mobile computing packages to get thinner. Using coreless ball grid array (BGA) substrates decreases the overall height of the component, but it presents manufacturing challenges and potential reliability concerns when subjected to thermal cycling. This study presents results from tests performed on a coreless 25 mm by 27 mm BGA package with a relatively large die and stiffener ring that survived over 8,000 temperature cycles without failure. In order to investigate the reason behind this robust performance the coefficient of thermal expansion (CTE) of the part was measured using digital image correlation (DIC). The DIC results indicated that this combination of die size, package size, and stiffener ring reduces the CTE mismatch between the BGA package and printed circuit board (PCB).
Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications
2008 58th Electronic Components and Technology Conference, 2008
For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC-PLGA) package to support low and mid range server solutions. This organic 50 mm x 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 x 16 mm) and a memory cache (15 x 13 mm) in a single piece lid capping solution.
Plastic ball grid array (PBGA) overview
Materials Chemistry and Physics, 1995
As integrated circuit functionality and clock speed continue to rise, innovative packaging approaches are in great demand. Recently, the plastic ball grid array (PBGA) technology has been gaining industry-wide interest and commitment as the potentially lowest-cost package for high-I/O devices and even for some lower-pincount applications. Drivers include the density advantages of an area array, quickly achieving six-sigma assembly yields with existing assembly equipment, the potential for excellent electrical and thermal performance, along with the traditional low cost of plastic packages. Because some perceived weaknesses are being eradicated, worldwide evaluation of the PBGA has accelerated. Although various aspects of this technology are discussed frequently, an overall assessment is still under development. In this paper, a systematic and comprehensive evaluation of PBGA technology will be described to identify (1) its technical advantages and limitations, (2) unique application areas where PBGA is the package of choice, and (3) current major hurdles for acceptance of PBGA and possible approaches to overcome these problems. The PBGA will be compared with PQFP, CQFP and CBGA in terms of package characteristics and their impact on system assembly. The characteristics include package attributes (i.e., package size, I/O counts and lead pitch), performance (i.e., electrical, thermal) and reliability (moisture). At the system level, solder joint fatigue, board routing, solder assembly yield, solder reparability and board delay are key metrics. The cost implication of various package families will be discussed. By analogy with SMT, the infrastructure for PBGA will take time to develop. The key elements and the current status of this infrastructure will be discussed.
Energies
The concept of a single-input/multi-output thermal network was proposed by the Development of Libraries of Physical models for an Integrated design environment (DELPHI) consortium more than twenty years ago. The present work highlights the recent improvements made to efficiently derive a low-computing-effort model from a fully detailed numerical model and to characterize its performances. The temperature predictions of a deduced ball-grid-array (BGA) dynamic compact thermal model are compared to those of a realistic three-dimensional representation, including the large set of internal copper traces, as well as its board structure, which has been validated by experiment. The current study discloses a method for creating an amalgam reduced-order modal model (AROMM) for that electronic component family that allows the preservation of the geometry integrity and shortening scenarios computation. Typically, the AROMM method reduces by a factor of 600 the computation time needed to obtain ...
Study of the Effect of Humidity on Thermal Cycling of a Ball Grid Array (Bga) Package
2018
I would take an opportunity to thank my professor and mentor Dr Dereje Agonafer for giving me this opportunity to work under his guidance. His words of wisdom were always a source of motivation to me throughout my research work. I would like to thank Dr Abdolhossein Haji Sheikh for the valuable time and serving as a committee member for my thesis. I would also thank Pavan Rajmane PhD. who helped me within the scope of this research work. His valuable knowledge and insights led me to complete the research work successfully. I would like to thank my team mates Anuraag Karnik and Pranav Nikam in the Reliability team who constantly motivated me to get this work done within the timeframe. It was a pleasure working with them. I would take this opportunity to thank my parents Mr. Terrence Ambosta and Rosebell Ambosta and sister Ms. Sarah Ambosta back at home because of which I came to the United States to pursue my master's degree. They were the pillars of my strength and driving force throughout the course of my work. I would also thank Ms. Ankita Lad for her constant words of motivation. I owe this renowned accomplishment of master's degree in mechanical engineering to God who has encouraged, helped and given me the strength to complete my research work.
2008 International Conference on Electronic Packaging Technology & High Density Packaging, 2008
Considerable research has been done on tracking ground targets, including on-road targets. Lane tracking of an on-road target is a new problem in the ground target tracking area. Knowledge of the lane that a target is located in is of particular interest in on-road surveillance and target tracking systems. This paper proposes a method to track the lane of an on-road target based on a Hidden Markov Model (HMM). It is assumed that an image sensor provides raw observation data. The formulation of the problem and our approach are given. Simulation results show that the implemented HMM-based lane estimators can achieve good performance.
Solder joint reliability of plastic ball grid array with solder bumped flip chip
Soldering & Surface Mount Technology, 2000
A computational parametric study on the solder joint reliability of a plastic ball grid array (PBGA) with solder bumped flip chip (FC) is presented. The basic configuration of the PBGA is 27mm package‐size and 1.27mm ball‐pitch. There were three kinds of ball population: four‐row perimeter grid array with/without thermal balls, and full grid array. A total number of 24 cases, involving various chip sizes, chip thicknesses and substrate thicknesses, were studied. The diagonal cross‐section of the PBGA‐printed circuit board (PCB) assembly was modeled by plane‐strain elements and was subjected to uniform thermal loading. Through mismatch of coefficient of thermal expansion (CTE), and lack of structural compliance, the solder joints were stressed to produce inelastic deformation. The accumulated effective plastic strain was evaluated as an index for the reliability of solder joints. The present study revealed the effects of aforementioned design parameters on the solder joint reliabilit...