The impact of battery capacity and memory bandwidth on CPU speed-setting (original) (raw)

Nonideal battery and main memory effects on CPU speed-setting for low power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001

This paper explores the system-level power-performance tradeoffs of dynamically varying CPU speed. Previous work in CPU speed-setting considered only the power of the CPU and only CPUs that vary supply voltage with frequency. This work takes a broader approach, considering total system power, battery capacity, and main memory bandwidth. The results, which are up to a factor of four less than ideal, show that all three must be considered when setting the CPU speed.

Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems

International Journal of Electrical and Computer Engineering (IJECE), 2018

Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3%-7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP. 1. INTRODUCTION Dynamic Voltage/Frequency Scaling (DVFS) has been used to reduce power consumption of computing systems. DVFS is a technique that increases or decreases the supply voltage by adjusting the operating frequency of CMOS circuits. CMOS circuits have static and dynamic power dissipation, and dynamic power dissipation is the dominant component in CMOS [1]. Most research on DVFS technique has focused on CPU DVFS [2], [3] because the CPU is the most power-consuming device when a computer system is actively running. Many contemporary OSs support DVFS of CPU. Linux's cpufreq [4] subsystem is an example. The frequency scaling technology is supported in hardware devices other than CPU such as the GPU or the memory bus, in such cases the operating frequency of the device can be managed by the user. For example, Linux system has a subsystem called devfreq to support frequency scaling of devices other than CPU [5]. Nexus 6 smartphone is a commercial mobile device supporting device frequency scaling, which allows us to adjust the clock speed of the memory bus that affects the memory bandwidth. Changing the frequency to access memory gives us another option to manage the power consumption of embedded systems. Attempts to manage the power consumption of memory access have been recently made. In [6], they proposed a DVFS method for DRAM based on memory bandwidth utilization. They devised a bandwidth-based frequency selection policy using their finding in experiments that memory latency is not significantly affected by the memory frequency at low bandwidth. But because memory hardware with DVFS support was not available, they emulated frequency scaling using timing delays. No DVFS is supported by DRAM so far because scaling of IO voltage on DRAM affects the stability and requires significant hardware change, but

EFFECT OF FREQUENCY SCALING ON POWER CONSUMPTION IN EMBEDDED SYSTEMS

transstellar Journals, 2022

Optimization of power consumption in a real time embedded systems is a critical design parameter. As most of low power embedded systems are battery operated and have very limited source of power. Therefore the optimization of power utilization is discussed in this paper establishing its relationship with execution frequency of core processing unit in multitasking environment. The number of processes required to be executed in multitasking embedded systems may vary with time for an application, and hence the dynamic power consumed also vary accordingly. Each process in real time are defined with respective absolute deadlines and their relative deadlines depend on the number of processes schedules at a time. The relative deadline parameter can be used to estimate the required operating frequency of processing unit and can be scaled accordingly to optimize the power consumption. The relative deadlines needs to be less than the absolute deadline for any process to complete the task successfully. Therefore the operating frequency can be dynamically scaled such that the relative deadlines are just within absolute deadlines. The hard-real time systems are designed to meet the deadline of all processes under maximum process load, hence the operating frequency of the processing unit is chosen much higher to complete make sure all the processes within deadline under peak load condition. However, scaling down the frequency under other conditions will improve the thermal stability and also optimize the power consumption. The analysis of frequency requirement is done for two most widely used scheduling methods, Earliest Deadline First (EDF) and Rate Monotonic (RM) scheduling algorithms for comparison.

A case study of a system-level approach to power-aware computing

ACM Transactions on Embedded Computing Systems, 2003

This paper introduces a systematic approach to power awareness in mobile, handheld computers. It describes experimental evaluations of several techniques for improving the energy efficiency of a system, ranging from the network level down to the physical level of the battery. At the network level, a new routing method based upon the power consumed by the network subsystem is shown to improve power consumption by 15% on average and to reduce latency by 75% over methods that consider only the transmitted power. At the boundary between the network and the processor levels, the paper presents the problem of local versus remote processing and derives a figure of merit for determining whether a computation should be completed locally or remotely, one that involves the relative performance of the local and remote system, the transmission bandwidth and power consumption, and the network congestion. At the processor level, the main memory bandwidth is shown to have a significant effect on the relationship between performance and CPU frequency, which in turn determines the energy savings of dynamic CPU speed-setting. The results show that accounting for the main memory bandwidth using Amdahl's law permits the performance speed-up and peak power versus the CPU frequency to be estimated to within 5%. The paper concludes with a technique for mitigating the loss of battery energy capacity with large peak currents, showing an improvement of up to 10% in battery life, albeit at some cost to the size and weight of the system.

Accurate Characterization of the Variability in Power Consumption in Modern Mobile Processors

2012

The variability in performance and power consumption is slated to grow further with continued scaling of process technologies. While this variability has been studied and modeled before, there is lack of empirical data on its extent, as well as the factors affecting it, especially for modern general purpose microprocessors. Using detailed power measurements we show that the part to part variability for modern processors utilizing the Nehalem microarchitecture is indeed significant. We chose six Core i5-540M laptop processors marketed in the same frequency bins - thus presumed to be identical - and characterized their power consumption for a variety of representative single-threaded and multithreaded application workloads. Our data shows processor power variation ranging from 7%-17% across different applications and configuration options such as Hyper-Threading and Turbo Boost. We present our hypotheses on the underlying causes of this observed power variation and discuss its potenti...

HAPPE: Human and Application-Driven Frequency Scaling for Processor Power Efficiency

IEEE Transactions on Mobile Computing, 2013

Conventional dynamic voltage and frequency scaling techniques use high CPU utilization as a predictor for user dissatisfaction, to which they react by increasing CPU frequency. In this paper, we demonstrate that for many interactive applications, perceived performance is highly-dependent upon the particular user and application, and is not linearly related to CPU utilization. This observation reveals an opportunity for reducing power consumption. We propose HAPPE (Human and Application driven frequency scaling for Processor Power Efficiency), an adaptive user-and-application-aware dynamic CPU frequency scaling technique. HAPPE continuously adapts processor frequency and voltage to the learned performance requirement of the current user and application. Adaptation to user requirements is quick and requires minimal effort from the user (typically a handful of key strokes). Once the system has adapted to the user's performance requirements, the user is not required to provide continued feedback but is permitted to provide additional feedback to adjust the control policy to changes in preferences. HAPPE was implemented on a Linux-based laptop and evaluated in 22 hours of controlled user studies. Compared to the default Linux CPU frequency controller, HAPPE reduces the measured system-wide power consumption of CPU-intensive interactive applications by 25% on average while maintaining user satisfaction.

Reducing energy usage with memory and computation-aware dynamic frequency scaling

2011

Over the life of a modern computer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures -characterizations of the patterns of execution of each loop in an application. This application characterization is matched with a series of benchmark loops, which have been run on the target system and exercise it various ways. These benchmarks are intended to form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the best power-delay product to the benchmark that most closely resembles each application loop is the one chosen for that loop. The application's frequency management strategy is then permanently integrated into the compiled executable via static binary instrumentation. This process is lightweight, only has to be done once per application (and the benchmarks just once per machine), and thus is much less laborious than running every application loop at every possible frequency on the machine to see what the optimal frequencies would be. Unlike most frequency management schemes, we toggle frequencies very frequently, potentially at every loop entry and exit, saving as much as 10% of the energy bill in the process. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.

Power Efficiency Study of Multi-threading Applications f or Multi-core Mobile Systems

One constant in computing which is true also for mobile computing is the continue requirement for greater performance. Every performance advance in mobile processors leads to another level of greater performance demands from newest mobile applications. However, on battery powered devices performance is strictly limited by the battery capacity, therefore energy efficient applications and systems have to be developed. The power consumption problem of mobile systems is in general a very complex one and remained very actual for quite a long time. In this paper we aim to define a software execution framework for mobile systems in order to characterize the power consumption profile of multi-threading mobile applications. Study results for different thread libraries, multi-core processors and multithreaded parallelized applications are also presented.

Energy-efficient CPU frequency control for the Linux system

Efficiency of energy usage in computing systems improves, however, still not at the rate matching the climbing demand for computing capacity. To address this urging problem, computing elements of the latest generation, that is, CPUs/graphics processing units, memory units, and network interface cards, have been designed to operate in multiple modes with differentiated energy consumption levels. Mode switching and high-frequency performance monitoring functions have also been exposed by co-designed abstract programming interfaces. The challenge of energy-efficient computing is to develop hardware control mechanisms taking advantage of the new capabilities. This paper aims at giving an insight into the structure of optimal energy-aware CPU frequency scaling rules. It gives a characterization of solutions to the optimal control problem of energy-efficient real-time packet inspection performed by a Linux server. A class of CPU frequency switching rules, exploiting dynamic voltage and frequency scaling mechanisms, is constructed based on experimentally identified model of server operations. The control rules are demonstrated to outperform the default CPU frequency scaling governor for the Linux kernel, both in terms of achievable power savings and service quality.