Aging and performance sensor for SRAM (original) (raw)

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

2012 13th Latin American Test Workshop (LATW), 2012

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static...

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

IEEE Transactions on Device and Materials Reliability, 2014

The threshold voltage drifts induced by positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin, and performance. This paper presents a low area overhead adaptive body bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependence of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, the READ SNM degradation by 12.24%, the WRITE margin degradation by 2.16%, the READ delay by 28.68%, and the WRITE delay by 32.61% compared to the conventional SRAM cell at 108 s aging time.

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Journal of Electronic Testing, 2014

The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs' aging during the SoC's lifetime based on the insertion of On-Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor's capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor's overheads is presented.

Analysis of SRAM metrics for data dependent BTI degradation and process variability

Integration, 2020

Bias Temperature Instability (BTI) is one of the most crucial reliability issues in modern CMOS technology. It leads to shift in device parameters, which eventually affect circuit performance. SRAM is a widely used circuit which occupies a considerable area in microprocessors. Hence it is important to understand the impact of BTI on performance/stability of SRAM. As device degradation due to BTI depends on gate activity, SRAM performance strongly depends on the data stored in the cell. In this paper, the gate activity is incorporated by activity factor 'α' which takes into account the various data patterns stored in the cell. Although many studies have reported the impact of BTI on SRAM performance, none focused on the worst degradation scenario. Our analysis with varying activity factor 'α' provides an opportunity to identify the data pattern for worst case degradation. Shift in threshold voltage due to BTI is modelled according to continuous and non-continuous applied gate bias, using physics-based compact model. Process variability is incorporated using Monte Carlo (MC) simulations and worstcase degradation at distribution tail is identified. In this paper, we consolidate various SRAM performance metrics from literature over the last three decades and demonstrate the impact of BTI and process variability with activity factor 'α' on these metrics.

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure. Index Terms-Gate oxide breakdown (GOBD), on-chip monitor, reliability, testing.

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Fifteenth International Symposium on Quality Electronic Design, 2014

This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

Analysis of process variation's effect on SRAM's read stability

In this paper we analyze the effect of manufacturing process variations on the SRAM stability in the read operation. We analyze the SRAM's read operation and the DC voltage-transfer characteristics (VTCs). Based on the VTCs, we define the read margin to characterize the SRAM cell's read stability. We calculate the read margin based on the transistor's current model using the BSIM3v3 model. Experimental results show that the read margin accurately captures the SRAM's read stability as a function of the transistors threshold voltage and the power supply voltage variations.

Effects of process variation on the access time in SRAM cells

2013

As technology advances continue reducing transistor features, microscopic variations in number and location of dopant atoms in the channel region induce increasing electrical deviations in device parameters such as the threshold voltage. Deviations refer to mismatches with respect to device parameters at design time. These deviations are specially important in SRAM cells whose transistors are constructed with minimum geometry to fulfill area constraints, since they can cause some cells to fail. In this paper, we study the impact of threshold voltage variations in the stability of the cell for a 16nm technology node. The failure probability has been studied for the four types of SRAM failures: write, access, read, and hold. We found that, under the assumed experimental conditions, the two former types of failures can be reduced by increasing the wordline pulse width of the cell. Experimental results show that access failures can be reduced up to 43.9% and write failures around 23.4% by enlarging the wordline pulse by 5 times the nominal width.

ARIA: Additive ReRAM-based Integrity and Aging Monitoring for ICs

IEEE Access

This paper reports an approach for monitoring aging and integrity of CMOS circuits through additively manufactured Resistive Random-Access Memory (ReRAM) based test structures. MgO-based ReRAM devices demonstrated excellent temperature sensing and aging modalities with simultaneous storage of sensed temperature and age as a change in the resistive state. The Process Voltage Temperature (PVT) characteristics, aging, and temperature sensitivity of MgO-ReRAM devices were experimentally studied and modeled to capture resistance distributions and temperature-based modalities. This inmemory sensing feature of ReRAM was integrated with specially designed read circuitry using 180 nm CMOS technology, to produce a measurable change in spiking-frequency over the lifetime of the ReRAM under normal aging conditions with the underlying CMOS circuits. Large feature sizes were used so these circuits can be fabricated in-house in trusted foundry. Temporal changes in temperature of underlying CMOS circuit could be captured by instantaneous change in resistive state of ReRAM with local temperature fluctuations which translated to a change in read circuit output. The characteristics of this circuit is studied in detail using simulations. Due to additive integration of ReRAM and associated circuitry, this approach for aging and integrity monitoring (AIM) ensures large spatial and accurate temporal monitoring of underlying CMOS die with minimal loss of the functional chip area for these added security features. The passive, in-memory sensing, and non-volatile nature of ReRAM also ensures low-power consumption in these circuits. The devices resistance states and material composition are specific to every device preventing reverse engineering and tampering of the devices, thus making it an attractive approach for adding customized security and trust features in advanced CMOS nodes-based circuits.

Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing

2015 IEEE International Reliability Physics Symposium, 2015

Extended 6 Transistors (6T) SRAM (Static Random-Access Memory) characterization is used to measure degradation while separating intrinsic from extrinsic yield and accounting for yield assessment challenges such as voltage drop and measurement variability. Separation of extrinsic yield pre-and post-stress reveals weak yield fixes and reduces HTOL (High Temperature Operating Life) failure risk.