CMOS-Compatible Through Silicon Vias for 3D Process Integration (original) (raw)

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

IEEE Journal of Solid-state Circuits, 2006

System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two-and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example.

Through silicon via technology — processes and reliability for wafer-level 3D system integration

2008 58th Electronic Components and Technology Conference, 2008

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the socalled ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, highperformance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBES®) is a typical example for the need of such mixed approaches.

Technologies for 3D wafer level heterogeneous integration

3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Ibm Journal of Research and Development, 2008

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added timeto-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with leadfree solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 lm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mX.

Sloped Through Wafer Vias for 3D Wafer Level Packaging

2007

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Low Electrical Resistance Silicon Through Vias: Technology and Characterization

56th Electronic Components and Technology Conference 2006, 2006

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures, which combine disparate technologies. In particular, when several die have to be connected in a small package, stacking would appear to be the best solution. However, this 3D packaging approach has to satisfy the constraints of high interconnection density and high data throughput in conjunction with good signal integrity, and reliability while maintaining a low cost. Today, several different approaches have been developed in order to perform 3D packaging. These include technologies like SiP (System in Package), SoC (System on Chip) or SoP (System On Package) [1]. A new concept for heterogeneous integration has been developed by CEA-LETI and is called SoW (System On Wafer) .

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

IBM Journal of Research and Development, 2000

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

2004

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, even though TSVs have great potential, there are many fabrication issues that must be considered. The rationale for systems based on TSVs, and a fabrication process development plan for the creation of these structures, was presented by S. Spiesshoefer et al. (see ECTC Proc., p.631-33, 2003). The development plan included five main areas for TSV fabrication: formation of the blind vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and wafer backside processing. The project goal is to create high aspect ratio vias four to six microns in diameter on 20-micron pitch in wafers that are subsequently thinned to a thickness of 15 to 20 microns. This paper will discuss the results obtained during the TSV fabrication in detail and explain the process development decisions that were made.

High Aspect Ratio Through-Wafer Interconnect for Three Dimensional Integrated Circuits

2005

In this work, we examine deep silicon copper interconnect related failure mechanisms due to deep silicon via etching based on BOSCH process. Though it is the best candidate for performing deep and high aspect ratio silicon etching, its cyclical nature of doing series of etch and passivation process creates very rough sidewall thus impacting the electrical performance of through-wafer copper interconnection. In the present work we have designed a dedicated test vehicle to study and evaluate the deep silicon via etch induced defects such as sidewall scallops, conformality of dielectric isolation and copper diffusion barrier over the entire depth of the via. In addition, thermo-mechanical simulation has been done to identify the potential weak sites to help us to zoom into possible failures sites.