A Novel Design of Full Adder Using Efficient Mux In QCA (original) (raw)

Novel Design of Full Adders using QCA Approach

World Academy of Research in Science and Engineering, 2019

This paper presents a novel design of full adder using QCA approach. It is one of the stand-in technologies introduced as a renewal key to the fundamental limits faced by CMOS technology. Some of the consequences of CMOS technology are their such as high ON/OFF speed, complexity, area and power consumption which are essential to replace with new technology like QCA. By using basic operators like majority gate and an inverter, other logic gates can be designed. Full adders place a major role in computational systems. In this work, 1-bit full adder is mapped out with minimum no. of cells by utilizing cell minimization technique. These circuits are simulated, imitated and verified for their proper output by utilizing QCA designer 2.0.3 tool.

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

International Journal of Theoretical Physics, 2018

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.

A Novel Design of Half and Full Adder using Basic QCA Gates

International Journal of Computer Applications, 2014

This paper presents the novel design of half adder and full adder using reduced number of QCA gates.This design utilizes the unique characteristics of QCA to design a half and a full adder.The basic component of QCA is a cell consisting of two electrons and four logically interacting quantum dots.Simulation indicates a fast,efficient and very attractive performance(i.e.complexity,area and delay)

Presenting a New Efficient QCA Full Adder Based on Suggested MV32 Gate

International Journal of NanoScience and Nanotechnology, 2016

Quantum-dot Cellular Automata (QCA) technology is a solution for implementation of the nanometer sized circuits and it can be a suitable replacement for CMOS. Similar to CMOS technology, designing the basic computational element such as adder with the QCA technology is regarded as one of the most important issues that extensive researches have been done about it. In this paper, a new efficient QCA full adder based on proposed MV32 gate is introduced which its novel structure leads to proper design technique selection and also its arrangement makes it very suitable. The proposed QCA full adder has 31 cells and its outputs are generated after the 0.75 of a clock time period. The proposed full adder is simulated using the QCADesigner2.0.3 simulation tool and has been compared with former works. The simulation results show that the proposed QCA full adder in terms of the number of used cells and occupied area is so better than others.

Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs

Electronics, 2021

Quantum-dot cellular automata (QCA) technology is considered to be a possible alternative for circuit implementation in terms of energy efficiency, integration density and switching frequency. Multiplexer (MUX) can be considered to be a suitable candidate for designing QCA circuits. In this paper, two different structures of energy-efficient 2×1 MUX designs are proposed. These MUXes outperform the best existing design in terms of power consumption with approximate reductions of 26% and 35%. Moreover, similar or better performance factors such as area and latency are achieved compared to the available designs. These MUX structures can be used as fundamental energy-efficient building blocks for replacing the majority-based structures in QCA. The scalability property of the proposed MUXes is excellent and can be used for energy-efficient complex QCA circuit designs.

Low Power and High Speed Multiplexer based adder

Full adder is a basic building block of many application specific integrated circuits. The paper evaluates and compares the performance of various full adder circuits which are designed using techniques such as XOR, transmission gates, multiplexers etc. Also a full adder circuit designed using multiplexer is proposed. The performance of these circuits is based on 180nm process model at supply voltage of 2.5V. The TSPICE simulation results show that the proposed circuit’s performance is better as compare to the circuits that are found in literature whose performance is evaluated.

A novel multiplexer-based low-power full adder

Circuits and Systems …, 2004

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

An ultra-low complexity of 2:1 multiplexer block in QCA technology

Indonesian Journal of Electrical Engineering and Computer Science, 2021

The limitations related to CMOS such as power consumption and parasitic capacitance lead scientists to search for new technologies. Quantum-dot cellular automata (QCA) is a CMOS alternative technology that uses charges instead of voltage level for binary representation. In QCA, many metrics are used for circuit differentiation such as delay, complexity and area. In this work, a new simple block of 2:1 QCA-Multiplexer is proposed. The proposed block is more efficient than previous designs by 0.43%, 0.53%, 50% and 0.72 in terms of area, complexity, delay and cost. QCADesigner software is used to design and verify the proposed circuit.

Design and Comparison of Full Adder Using TG Based 4:1 MUX

https://www.ijrrjournal.com/IJRR\_Vol.9\_Issue.11\_Nov2022/IJRR-Abstract15.html, 2022

The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder.

An Efficient Layout of Single-Layer Full Adder Using QCA

Advances in Intelligent Systems and Computing

Quantum cellular automata (QCA) is a new method of computation used in designing of electronic digital circuits at scale of nanometers. QCA has been used to achieve better performance in cell density, high switching speed and low power dissipation. An adder is a very useful component used for designing of arithmetic digital devices. This paper presents a layout of full adder designed on single layer which is efficient in various aspects based on QCA technology proposed. The goal of the research is to minimize the cells used, designed area and delay in designing of full adder based on QCA. The proposed layout of full adder has been efficient in number of cells used, designed area as well as latency in clocks. The proposed layout has been designed using XOR gate and majority voter. The proposed layout of adder consist of 24 cells with an optimized area of 0.016 µm 2 and 2-clock phases (~0.125 ps) which shows more efficient from previous work on adders. The layout of full adder has been successfully designed and simulated using QCADesigner-E 2.2.