Carbon nanotube circuits in the presence of carbon nanotube density variations (original) (raw)
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Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011
Variations in the spatial density of carbon nanotubes (CNTs), resulting from the lack of precise control over CNT positioning during chemical synthesis, is a major hurdle to the scalability of carbon nanotube field effect transistor (CNFET) circuits. Such CNT density variations can lead to non-functional CNFET circuits. This paper presents a probabilistic framework for modeling the CNT count distribution contained in a CNFET of given width, and establishes the accuracy of the model using experimental data obtained from CNT growth. Using this model, we estimate the impact of CNT density variations on the yield of CNFET very large-scale integrated circuits. Our estimation results demonstrate that CNT density variations can significantly degrade the yield of CNFETs, and can be a major concern for scaled CNFET circuits. Finally, we analyze the impact of CNT correlation (i.e., correlation of CNT count between CNFETs) that exists in CNT growth, and demonstrate how the yield of a CNFET storage circuit (primarily limited by its noise immunity) can be significantly improved by taking advantage of such correlation.
Carbon nanotube circuits: Living with imperfections and variations
2010
Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon CMOS. However, CNFET circuits are subject to several sources of imperfections. These imperfections lead to incorrect logic functionality and substantial circuit performance variations. Processing techniques alone are inadequate to overcome the challenges resulting from these imperfections. An imperfection-immune design methodology is required. We present an overview of imperfection-immune design techniques to overcome two major sources of CNFET imperfections: metallic Carbon Nanotubes (CNTs) and CNT density variations.
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement
2010
Carbon Nanotubes (CNTs) are grown using chemical synthesis, and the exact positioning and chirality of CNTs are very difficult to control. As a result, "small-width" Carbon Nanotube Field-Effect Transistors (CNFETs) can have a high probability of containing no semiconducting CNTs, resulting in CNFET failures. Upsizing these vulnerable smallwidth CNFETs is an expensive design choice since it can result in substantial area/power penalties. This paper introduces a processing/design co-optimization approach to reduce probability of CNFET failures at the chip-level. Large degree of spatial correlation observed in directional CNT growth presents a unique opportunity for such optimization. Maximum benefits from such correlation can be realized by enforcing the active regions of CNFETs to be aligned with each other. This approach relaxes the device-level failure probability requirement by 350X at the 45nm technology node, leading to significantly reduced costs associated with upsizing the small-width CNFETs.
—This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nan-otube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic CV /I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15–20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. Index Terms—Analytical model, carbon nanotube (CNT), carbon-nanotube field-effect transistor (CNFET), compact model, performance benchmarking, screening effect, SPICE.
Optimizing the Performance of Carbon Nanotube Transistors
2006 Sixth IEEE Conference on Nanotechnology, 2006
A numerical study of carbon nanotube field effect II. APPROACH transistors is presented. The non-equilibrium Green's function In this section the models used to study the static and formalism was employed to investigate the static response. Based d on the quasi-static approximation, the dynamic response has been dynamic response of CNTFETs are explained. determined. The effect of the gate-source and gate-drain spacers A. Static Response on the static and dynamic response of the device was studied. Simulation results suggest that both the dynamic and static Based on the NEGF formalism we studied the effect of characteristics of the device can be improved by appropriately device geometry on the performance of carbon nanotube fielddesigning the gate-source and gate-drain spacers.
Carbon Nano-tube Field Effect Transistor (CNFET) is one of the most promising successors of CMOS technology because of its superb electrical features. Although these features are proper for implementing in various practical circuits, CNFET-based circuits will encounter enormous fabrication problems due to their size. Two of the most challenging problems are timing yield and reliability reduction. Consequently methods for improving robustness of CNFET-based circuits should be conducted. Considering these problems, in this paper, the statistical model of reliability and timing yield of CNFET-based circuits is presented and then we propose a statistical driven correlation-aware placement for CNFET-based gates. We illustrate that our placement engine improves the reliability and timing yield of various circuits. Following these observations, in our method, a statistical approach is conducted to get optimum timing yield of register-to-register path in a sequential circuit. Subsequently, experimental results show improvement of about 19% in timing yield and 17% in reliability of some ISCAS89 circuits.
Variability and Reliability of Single-Walled Carbon Nanotube Field Effect Transistors
Excellent electrical performance and extreme sensitivity to chemical species in semiconducting Single-Walled Carbon NanoTubes (s-SWCNTs) motivated the study of using them to replace silicon as a next generation field effect transistor (FET) for electronic, optoelectronic, and biological applications. In addition, use of SWCNTs in the recently studied flexible electronics appears more promising because of SWCNTs' inherent flexibility and superior electrical performance over silicon-based materials. All these applications require SWCNT-FETs to have a wafer-scale uniform and reliable performance over time to a level that is at least comparable with the currently used silicon-based nanoscale FETs. Due to similarity in device configuration and its operation, SWCNT-FET inherits most of the variability and reliability concerns of silicon-based FETs, namely the ones originating from line edge roughness, metal work-function variation, oxide defects, etc. Additional challenges arise from the lack of chirality control in as-grown and post-processed SWCNTs and also from the presence of unstable hydroxyl (-OH) groups near the interface of SWCNT and dielectric. In this review article, we discuss these variability and reliability origins in SWCNT-FETs. Proposed solutions for mitigating each of these sources are presented and a future perspective is provided in general, which are required for commercial use of SWCNT-FETs in future nanoelectronic applications.
IEEE Transactions on Nanotechnology, 2009
Conventional CMOS technology provides a lot of opportunities in the field of electronics device. But presently, carbon nanotube field effect transistor (CNTFET) is a new technology for the application in the field of electronic device. Due to the limitation of the size of CMOS, CNTFETs are the promising substitute due to its nano scale size. CNTFET also shows the high stability, low power circuit design, high signal to noise margin (SNM) and high gain in the circuit design. A novel design of CNTFET based inverter with an optimum chiral vector is proposed in this paper. PSPICE platform is used to model and simulation this CNTFET inverter circuit. The proposed CNTFET inverter circuit is investigated based on noise margin characteristics. A maximum voltage gain of 45dB is observed from NCNTFET of the inverter and a high noise margin of 400mV and a low noise margin of 309mV are achieved from the proposed inverters. This approach is a useful technique for fabricating integrated logic devices and circuits based on CNTFETs.
Effect of carbon nanotube network morphology on thin film transistor performance
Nano Research, 2012
The properties of electronic devices based on carbon nanotube networks (CNTNs) depend on the carbon nanotube (CNT) deposition method used, which can yield a range of network morphologies. Here, we synthesize single-walled CNTs using an aerosol (floating catalyst) chemical vapor deposition process and deposit CNTs at room temperature onto substrates as random networks with various morphologies. We use four CNT deposition techniques: electrostatic or thermal precipitation, and filtration through a filter followed by press transfer or dissolving the filter. We study the mobility using pulsed measurements to avoid hysteresis, the on/off ratio, and the electrical noise properties of the CNTNs, and correlate them to the network morphology through careful imaging. Among the four deposition methods thermal precipitation is found to be a novel approach to prepare high-performance, partially aligned CNTNs that are dry-deposited directly after their synthesis. Our results provide new insight into the role of the network morphologies and offer paths towards tunable transport properties in CNT thin film transistors.
IEEE Transactions on Electron Devices, 2006
Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential.