Design & Implementation of 8x8 Multiplier Unit using MT-CMOS Technique (original) (raw)

Power and Speed Analysis of CMOS-based Multipliers using VEDIC techniques

Multipliers are one of the most important components in design of both digital and analog circuits. The design and structure of multipliers play a significant role to determine speed and power consumption of processing units as the core component of electronic devices. In this paper, we design 4×4 and 8×8 multipliers in layout level to extract important design parameters. VEDIC mathematic techniques and CMOS logic are used to obtain a tradeoff between speed and power efficiency. Our results show that voltage range between 1.5v and 2.5v is the efficient range to perform high speed and low power multiplication.

VLSI ARCHITECTURE OF AN 8-BIT MULTIPLIER USING VEDIC MATHEMATICS IN 180NM TECHNOLOGY

A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation.

DESIGN OF LOW POWER AND HIGH SPEED GDI BASED 8-BIT VEDIC MULTIPLIER

ANVESAK, 2023

Multiplier is the common hardware block present in any processor. Speed and power consumption become very vital in multiplier design consideration to conserve energy. An 8 bit Vedic multiplier using GDI technique is designed in this paper. Multiplication of two numbers will take more time and many steps. To design the proposed multiplier the Vedic mathematics sutra called UT is used. Any logic circuit can be designed by using CMOS logic. The CMOS logic will consumes more area. The numbers of transistors in the circuit are reduced by using GDI logic. Thus the Vedic mathematics will reduce the delay and the GDI logic will reduce the transistors count in a circuit which in turn reduces the power.

A Transistor Level Analysis for a 8-BIT Vedic Multiplier

International Journal of Electronics Signals and Systems, 2012

Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed mu...

Design of Multiplier using Low Power CMOS Technology

The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.

Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier

— In today scenario digital circuits are become more and more complex because of long arithmetic calculations but with the help of Vedic mathematics that calculations can become easy and fast. To make multiplier we have different techniques, in this paper we design 16x16 CMOS multiplier using Vedic mathematics technique.

Low Power High Performance 8bit Vedic Multiplier Using 16nm

International Journal of Emerging Trends in Engineering Research, 2023

In this paper, an 8-bit Vedic multiplier is designed. The performance of the system basically works better if the performance of the multiplier is good. In today's digital time, Multiplier is one which consumes power at the same time speed of multiplier is playing very important aspects in this. Multiplier Optimization for power and delay both will play an important role. Adders such as Ripple carry adder and carry look-ahead adder and carry skip adder are also having a role in the selection of adder units in the multiplier. Here all the three adders are designed using transmission gates and compared using CMOS.

Implementation of Low Power and Area Efficient Vedic Multiplier

International Journal of Innovative Technology and Exploring Engineering, 2019

Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.

Low Power High Performance Multipliers using MTCMOS Technique

This paper presents the power and delay optimized multipliers utilizing MTCMOS technique. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). Three 8 bit multipliers i.e. Array, Braun and Baugh Wooley has been constructed on Cadence Virtuoso and results have been compared on the basis of power, delay and leakage. All the simulations have been carried out on 45nm technology.