Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment (original) (raw)
Related papers
Analog Integrated Circuits and Signal Processing, 2014
This paper presents the design and Silicon verification of a 2.488-11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps.
SFI-4.1 16-Channel SDR Interface with Bus Alignment Using Virtex-6 FPGAs
2010
This application note describes an SFI-4.1 reference design that implements the OIF-SFI4-01.01 interface [Ref 1], a 16-channel, source-synchronous LVDS interface operating at single data rate (SDR). The transmitter (TX) requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The transmitter operates at 4:1 serialization on each of the 16 data channels. The receiver (RX) also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input. The receiver operates at 1:4 deserialization on each of the 16 data channels. The timing of the receiver is described in depth and is characterized in hardware.
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
The paper presents the design of a 2.488 -11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a lowjitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.
2 Gbps SerDes Design Based on IBM Cu-11 (130nm) Standard Cell Technology
2008
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a “Statistical Random Sampling Technique ” to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data sym...
POWER EFFICIENT SERDES TRANSCEIVERS FOR HIGH-SPEED SERIAL COMMUNICATION– REVIEW
IAEME PUBLICATION, 2021
A SerDes is a transceiver with an integrated circuit (IC or chip) that converts parallel data into serial data and vice versa. SerDes has generally been used in the high-speed serial interface for the past few years and is widely used as an ASIC type and explicitly standard part of the application. Use both frequency adjustment and jitter as components. However, the actual incentive for a particular ser/des must be estimated experimentally. Intermediate frequency behavior Interactions in the IF range are generally complex. With technology slowdowns and processing speeds increasing, electrical connections are seen as a bottleneck for high-speed signal transmission between chips. The wide range of SerDes drive covers large distances at multi-gigabit speeds with a simple FPGA interface. A ser/des is a pair of functional squares commonly used in high-speed communications. The paper surveys with the SERDES technology for networking capacity regions. A data switch concept is presented to illustrate the intended useful backplane and switch SERDES ICs.
An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility
2008 IEEE Asian Solid-State Circuits Conference, 2008
A small area PHY transceiver that is compatible with CEI6G-LR, CEI6G-SR, SAS-6G, PCIe and XAUI standards is demonstrated. The 4-channel transceiver is realized in a 90nm CMOS process with each channel occupying a die area of 0.325mm 2. Power dissipation per channel is less than 230mW from a 1V supply for 6.25Gb/s, and scales for data rates down to 1.25 Gb/s.
2005
It may be predicted now, even assuming very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals. The paper presents the idea and realization of a gigabit synchronous data distributor designed to work in the LLRF control system of TESLA technology based X-ray FEL. The design bases on a relatively simple and cheap FPGA chip Cyclone. Commercially available SERDES (serializer/deserializer) and optical transceiver chips were applied. The optoelectronic module is embedded on the main LLRF BMB (backbone mother board). The MB provides communication with the outside computer control system, programmable chip configuration, integration with other functional modules and power supply. The hardware implementation is here described and the used software for BER (bit-error-rate) testing of the multi-gigabit optical link. The measurement results are presented. The appendix contains a comparison between the available protocols of serial data transmission for FPGA technology. This TESLA Technology Report is a partial contribution to the next version of the SIMCON system which is expected to be released this year. The SIMCON, ver 3. will contain 8 channels and multi-gigabit optical transmission capability.
Design of Fixed One-Bit Latency Serdes Transceiver
Today's communication world experiences a maximum amount of problems linked with serial interconnects since they occupy the entire communication field, therefore the serializer/deserializer (SerDes) devices make huge changes in the market with large differences in cost and performance. But they fail to maintain constant communication latency throughout the transmission after each reset or power up. In this paper a fixed one bit latency serdes transceiver is proposed which is built using delay tuning and phase shifting technologies. It overcomes the shortcomings of buffering and delays generated by clocks. A specific implementation based on Xilinx Spartan 6 FPGA is presented in this paper. The results indicate that the device achieves a constant latency with improvements in buffering each time after reset.
High speed serial transceivers for data communication systems
IEEE Communications Magazine, 2001
The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards.