Mobility based Net Ordering for Simultaneous Escape Routing (original) (raw)

Simultaneous Escape Routing using Network Flow Optimization

Malaysian Journal of Computer Science

With the advancement in technology, the size of electronic components and printed circuit boards (PCB) is becoming small while the pin count of each component is increasing. This has necessitated the use of ball grid array (BGA) type of components where pins are attached under the body of component as a grid. The problem of routing pins from under the body of component to the boundary of the component is known as escape routing. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant PCB design. The task of SER is non-trivial, given the small size of components and hundreds of pins arranged in random order in each component that needs ordered connectivity. In this paper, first we propose flow models for different inter pin capacities. We then propose linear network flow optimization model that simultaneously solves the net ordering and net escape problem. The model routes maximum possible nets between two components of the PCB, by considering the design rules. Comparative analysis shows that the proposed optimization model performs better than the existing routing algorithms in terms of number of nets routed.

New optimal layer assignment for bus-oriented escape routing

Integration, 2012

It is known that the increase of the pin count makes escape routing difficult in PCB designs. Based on the optimal feature of a left-edge algorithm for interval packing, a modified left-edge algorithm is proposed to optimally solve the layer assignment problem for bus-oriented escape routing. Firstly, a set of assignment constraints is generated for the overlapping relations of the left or right projection intervals and the crossing relations of all the buses between two adjacent pin arrays. With the consideration of the assignment constraints, a modified left-edge algorithm is further proposed to minimize the number of the used layers and assign all the buses onto the used layers. Compared with the Kong's heuristic algorithm [4], it is proved that our proposed optimal algorithm guarantees that the number of the used layers is minimized and the experimental results show that our proposed algorithm reduces 8.8% of the number of the used layers for eight tested examples on the average. Compared with the Yan's O(n 2.38) optimal algorithm [5], it is proved that our proposed optimal algorithm has better time complexity in O(n 2) time and the experimental results show that our proposed algorithm reduces 46.5% of CPU time for eight tested examples on the average.

Escape routing for staggered-pin-array PCBs

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011

To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggeredpin-array escape routing problem. Experimental results show that our approach successfully completed the routing for all testcases efficiently and effectively.

A new approach to routing of two-layer printed circuit board

International Journal of Circuit Theory and Applications, 1981

This paper presents a new method for routing two-layer printed circuit boards with fixed geometry, i.e. alternate columns of pins and vias. Circuit components are mounted on top of the board, and conductor wires are to be laid on the board such that circuit connections can be properly made. The proposed approach gives 100 per cent routability. The method consists of three steps, namely: partitioning of multi-pin nets into 2-pin subnets, via assignment, and routing on the tho layers. In comparison with the traditional unidirectional routing, the method offers more flexibility and it requires usually about half as many vias. A computer program based on the presented algorithms was written. Its implementation is presented along with testing examples.

An efficient multi-layer diagonal router for multi-terminal printed circuit boards

Computers & Electrical Engineering, 1995

This paper presents a grid-based multi-layer, multi-terminal autorouter with the unique feature of diagonal routing. The router is suitable for routing memory boards and highly congested printed circuit boards. Diagonal routing is extremely useful in minimizing vias and in obtaining a high rate of completion with total route length reduced by up to 20% comparatively. The router employs an improved maze algorithm to incorporate multi-layer diagonal routing. The cost function used in the algorithm is complicated, but can be easily modified to meet specific needs. The algorithm models multi-terminal routing as a minimum spanning tree problem to use the least amount of wiring which is most desirable in the electronic industry. Intelligent net ordering and dynamic data structures reduce memory requirement and total route time by up to 30% compared to recently developed routers. The algorithm described in this paper was extensively tested against standard benchmarks and very inspiring results were achieved.

An algorithm for automated printed circuit board layout and routing evaluation

1993 International Symposium on Electromagnetic Compatibility, 2000

An ;iIgoritIiiii h;is Ixcn tlcvclol)cd to evalu;itc printed circuit hoards t1i;it :ire designed usiiig iiutoin;itcd Iwaril h y o u t ; i i d routing software. 1 lie ;tlgoriililii ;uialyzes ;ispc~~ts of colnpoiicnt pl;rceinent and trace routing whilc sc;irc.liiiig lor violations 0 1 Ixisic EMC design principles. The algorithin is iinpleiiicnicd in ;I ctxle designed t o work with ;i widely used hoard l a y~i u t ;inti routing 1)rt)gr;uii. This code cmi help novice and expcriciiccd circuit hoiird dcsigiicrs t o ;ivoid mistakes that niay result in serious clectroinagnetic comp;itihility prohleins. 1 1 A net is a circuit board trace that connects two or more compomnts. It is the physical equivalent of a node in a schematic diagram.

Placement and Routing in VLSI design Problem Using Single Row Routing Technique

2007

Two major problems are involved in VLSI design, namely, the placement of components and routing between these components. Single row routing problem is a combinatorial optimization problem of significant importance for the design of complex VLSI multi layer printed circuit boards (PCB's). The design involves conductor routing that makes all the necessary wiring and interconnections between the PCB modules, such as pins, vias, and backplanes. In very large systems, the number of interconnections may exceed tens of thousands. Therefore, we have to optimize the wire routing and interconnections and thus determine the efficient designs. Kernighan-Lin algorithm, traveling salesman problem, simulated annealing algorithm and single row routing problem are used to find the best design. Included here are some simple examples to find the results. A simulation program using Microsoft Visual C++ is developed to simulate the single row routing problem using the simulated annealing algorithm....

An analysis of wiring performances of a routing system for high density printed wiring boards

Electronics and Communications in Japan Part I-communications, 1982

Recent advances in the technology of microelectronics have changed the design rule for printed wiring boards, allowing the number of wiring tracks between consecutive pins of an ordinary dual in line package (DIP) to be two or more. When the wiring density augments to that extent, conventional routers are confronted with various difficulties.To cope with this situation, the single-row router which has topological fluidity can be employed in conjunction with the line-search router. We have already developed a new routing system constructed of a line-search router combined with a single-row router and of a maze-running router. However in each routing process there are many parameters, the combination of whose values have much influence on the wiring performance of the whole system.In this paper we outline this routing system, describe some experimental results in order to determine values of these parameters, and show that the analysis of implemented results suggests high performance for high density printed circuit boards (PWB's).

A new genetic algorithm for single row routing [of PCBs]

… of the 38th Midwest Symposium on, 1995

This paper presents a new genetic algorithm for single row routing (SRR). Unlike traditional algorithms, the new algorithm allows both tracks and doglegs to be minimized concurrently with a varying weight placed on each. The new algorithm is compared to existing algorithms for track and dogleg minimization. The results show that the algorithm effectively and simultaneously minimizes both doglegs and tracks.