A fully digital-compatible BIST strategy for ADC linearity testing (original) (raw)
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High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy
IEEE Transactions on Instrumentation and Measurement, 2009
This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three lowresolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to a ±0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.
BIST and production testing of ADCs using imprecise stimulus
ACM Transactions on Design Automation of Electronic Systems, 2003
A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitati...
A low-cost BIST architecture for linear histogram testing of ADCs
This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
2006
This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for system-on-a-chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals
IEEE Transactions on Instrumentation and Measurement, 2005
Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of 2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability.
IEEE Transactions on Very Large Scale Integration Systems, 2019
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On-chip ramp generators for mixed-signal BIST and ADC self-test
IEEE Journal of Solid-State Circuits, 2003
A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4 V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of 175 V. Experimental and theoretical results are in good agreement.
Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs
International Test Conference, 2003. Proceedings. ITC 2003.
As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for costeffective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).
A Maximum Likelihood Estimator for ADC and DAC Linearity Testing
2008
Ab st ra c t-The paper illustrates a method for simultaneous ADC and DAC linearity testing in a loopback scheme. The main features of the method are: (i) it is statistically nearly optimal, being based on a maximum likelihood estimator; (ii) it does not require prior knowledge neither of the ADC nonlinearity, nor of the DAC nonlinearity -both are simultaneously measured relying only on a constant-variance noise. The performances of the method are studied both mathematically and via computer simulations. The method, because of its optimality and universality, appears to be also a good candidate for inclusion in technical standards relevant to ADC and DAC testing.