Phase noise in multi-gigahertz CMOS ring oscillators (original) (raw)
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A Study of Phase Noise in CMOS Oscillators
This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-m CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB.
Jitter and phase noise in ring oscillators
IEEE Journal of Solid-State Circuits, 1999
A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and shortchannel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.
A Rigorous Phase Noise Analysis of Tuned Ring Oscillators
2007 IEEE Radio and Wireless Symposium, 2007
Tuned ring oscillators have found numerous applications due to their ability to generate multiple phases at high frequencies of operation while maintaining high signal purity. However, a comprehensive phase noise theory that explains the phase noise performance of tuned rings as a function of design parameters such as the number of elements and inter element phase shift is lacking. This paper rigorously builds such a theory and demonstrates that the phase noise improves by a factor of 10l100N as the number of elements (N) is increased. Further, the phase noise deteriorates (by a factor of 40loglocosAi at least) when the inter element phase shift AO is increased. In the context of multiple phase generation, under a fixed current budget, we demonstrate that it is beneficial to use a larger ring sizes. Extensive GHz-range simulations as well as measurements of prototype oscillators validate these claims.
A Low Phase Noise CMOS Ring Oscillator Using Phase Modulation and Pulse Injection Techniques
This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of-131.5 dBc/Hz @1MHz offset and FoM of-199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
Multi-phase ring oscillator with minimized phase noise for ultra-wideband applications
2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014
This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The proposed RO consumes only 3.6 mW from a 1.8V power supply while having an oscillation frequency of 5.5 GHz with a 330 MHz fine tuning range. This RO is employing the pulse injection technique for phase noise enhancement. It has a phase noise less than -133.5 dBc/Hz @ 1 MHz offset. It achieves a figure of merit (FoM) of -182.75 dBc/Hz .This RO is designed and simulated in the standard 0.18 μm CMOS technology.
A Low Phase Noise CMOS Ring Oscillator Using Phase Modulation and Pulse Injection Techniques (マイクロ波)
This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of -131.5 dBc/Hz @1MHz offset and FoM of -199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
Physics-Based Phase Noise Analysis of CMOS RF Oscillators
2006 International Conference on Simulation of Semiconductor Processes and Devices, 2006
A TCAD framework that can predict the phase noise spectrum of the oscillator using the nonlinear perturbation analysis is developed. The device-circuit mixed-mode simulation technique based upon the shooting-Newton method is exploited to evaluate the periodic steady-state solution of the oscillator. The influence of noise sources inside the devices on the phase deviation is calculated in an efficient and accurate way using the perturbation projection vector. The output power spectrum can be easily obtained in this framework. As its application, the output power spectrum of a CMOS LC voltage-controlled oscillator is calculated.
Phase noise in a differential CMOS voltage-controlled oscillator for RF applications
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000
This paper presents theoretical and experimental results on phase noise of differential CMOS oscillators. A simple analytical expression is derived and verified by simulation which relates the phase noise including the device excess noise factor to circuit parameters. In agreement with the theoretical results, an experimental 1.9-GHz oscillator yielded phase noise as low as −100 dBc/Hz at 100-kHz offset at a power consumption of 12 mW. A wide tuning range of 250 MHz was obtained by using PMOSFET's as varicap with only slight degradation of the phase-noise performance due to the varicap.
2009
Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pairbased ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.