Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics (original) (raw)
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Soft Breakdown in Ultrathin SiO2 Layers: the Conduction Problem from a New Point of View
Japanese Journal of Applied Physics, 1999
In this work, the soft breakdown failure mode in ultrathin (<5 nm) SiO 2 layers is experimentally examined by means of current-voltage measurements performed on samples with different gate areas, oxide thicknesses and substrate types. The observed astounding matching which exhibits some of these characteristics, as well as the common features with the final breakdown, leads us to suggest that the current flow in the analysed regime might be largely controlled by the extremely constrictive dimensions of the oxide leakage spots. We present an alternative explanation to the soft breakdown phenomenon which can be naturally extended to the final breakdown conduction stage. In order to illustrate our ideas, a qualitative comparison with the theoretical behaviour of a classical point contact system is also discussed.
On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers
IEEE Transactions on Electron Devices, 1998
In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate current and substrate current as a function of the gate voltage after SBD are stable and unique curves, but for smaller area devices both currents become lower and unstable. This difference can be explained by the different energy available for discharging in the SBD path. It is shown that the SBD detection strongly depends on the test structure area. In nMOSFET's for positive gate polarity, the large increase in the substrate current at the SBD moment is proposed as a sensitive SBD detector. Two level fluctuations in the gate current are investigated at different voltages and are explained by means of a model where electron capture-emission in the traps of the SBD path induces local field fluctuations causing variations in the tunneling rate across the oxide. In the substrate current directly correlated two-level fluctuations are observed.
Soft breakdown fluctuation events in ultrathin SiO2 layers
Applied Physics Letters, 1998
When an ultrathin ͑Ͻ5 nm͒ oxide is subjected to electrical stress, several soft-breakdown events can occur prior to the final dielectric breakdown. After the occurrence of such failure events, the current-voltage (I-V) characteristic corresponds to the superposition of highly conductive spots and background conduction through the undegraded capacitor area. In this conduction regime, the application of a low constant voltage gives rise to large leakage current fluctuations in the form of random telegraph signal. Some of these fluctuations have been identified with ON/OFF switching events of one or more local conduction spots, and not with a modulation of their conductance. The experimental soft-breakdown I-V characteristics are shown to be better understood if the spot conduction is considered to be locally limited by the silicon electrodes and not by the oxide.
Intrinsic dielectric breakdown of ultra-thin gate oxides
Microelectronic Engineering, 2001
We have investigated the dynamics of intrinsic dielectric breakdown (BD) in SiO thin films of thickness in the range 2 from 35 to 3 nm. BD is obtained under constant voltage Fowler-Nordheim stress at fields between 10 and 12.5 MV/ cm. As a function of oxide thickness we have followed with high time resolution the dynamics of the BD transient and analysed the post-BD damage by using transmission electron microscopy, photon emission microscopy and measurements of the post-BD current-voltage (I-V) characteristics. Moreover, the effect of the density of electrons at the cathode on the resulting BD damage is put in evidence. The data are interpreted and discussed in the framework of a model.
Micro breakdown in small-area ultrathin gate oxides
IEEE Transactions on Electron Devices, 2002
The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness OX = 3 2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at = +2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.
Reduction of thermal damage in ultrathin gate oxides after intrinsic dielectric breakdown
Applied Physics Letters, 2001
We have compared the thermal damage in ultrathin gate SiO 2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power threshold at the boundary between soft and hard breakdown, and they are compared to numerical simulations of heat flow.
IEEE Transactions on Electron Devices, 2005
The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.
Microelectronic Engineering, 1999
We present an alternative explanation for the soft (SBD) and hard (HBD) breakdown conduction modes in ultrathin gate oxides based on the physics of mesoscopic conductors. It is shown that the Landauer approach applied to this system not only gives the observed HBD conductance values, which are those expected for a ballistic constriction in the linear and nonlinear regimes, but also a plausible mechanism for the SBD conduction.
We have investigated the properties of soft breakdown (SBD) in thin oxide (4.5 nm) nMOSFETs with measurements of the gate and substrate leakage currents using the carrier separation technique. We have observed that, at lower gate voltages, the level of the substrate current exhibits a plateau. We propose that the observed plateau is due to the Shockley-Hall-Read (SHR) generation of hole-electron pairs in the space charge region and at the Si-SiO 2 interface. At higher voltages, the substrate current steeply increases with voltage, due to a tunneling mechanism, trap-assisted or due to a localized effective thinning of the oxide, from the substrate valence band to the gate conduction band, which becomes possible for gate voltages higher than the threshold voltage. The proposed interpretation is consistent with the results of measurements performed at different operating conditions, in the presence of light and in the case of substrate reverse bias. The presented results are also usefu...