Micro breakdown in small-area ultrathin gate oxides (original) (raw)
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On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers
IEEE Transactions on Electron Devices, 1998
In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate current and substrate current as a function of the gate voltage after SBD are stable and unique curves, but for smaller area devices both currents become lower and unstable. This difference can be explained by the different energy available for discharging in the SBD path. It is shown that the SBD detection strongly depends on the test structure area. In nMOSFET's for positive gate polarity, the large increase in the substrate current at the SBD moment is proposed as a sensitive SBD detector. Two level fluctuations in the gate current are investigated at different voltages and are explained by means of a model where electron capture-emission in the traps of the SBD path induces local field fluctuations causing variations in the tunneling rate across the oxide. In the substrate current directly correlated two-level fluctuations are observed.
A model of the stress induced leakage current in gate oxides
2001
A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress.
Modeling of Stress-Induced Leakage Current in Thin Gate Oxides
An analytic model of the stress-induced leakage current in thin gate oxides was developed under the assumptions that traps created in the gate oxide during high field injection of electrons have an exponential distribution in energy and transport of the ektrons Localized in the traps is due to an activated process of motion from one trap to another. The electric 6eld and temperature dependence of the leakage current in a wide range were explained successfully by the model.
Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability
Microelectronics Reliability, 2007
Gate oxide breakdown has been historically considered a catastrophic failure mechanism for CMOS technology. With CMOS downscaling the mid 1990's have seen the emergence of soft breakdown as a possible failure mode. At the same time the notion started appearing that the first breakdown event does not necessarily spell the immediate failure of the entire CMOS application. Relaxation of the CMOS circuit reliability criteria, however, requires a thorough understanding of the impact of the breakdown path on FET behavior. This cannot be consistently achieved without the microscopic perspective of the physical effects occurring in the affected device. Future CMOS applications will be able to sustain many soft breakdown events, which will be treated as additional parametric variation. Tools ranging from simulation to circuit monitoring will assure reliability at the functional level.
Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics
IEEE Transactions on Electron Devices, 2000
Prior to any attempt to model a charge transport mechanism, a precise knowledge of the parameters on which the current depends is essential. In this work, the soft breakdown (SBD) failure mode of ultrathin (3-5 nm) SiO 2 layers in polysilicon-oxide-semiconductor structures is investigated. This conduction regime is characterized by a large leakage current and by multilevel current fluctuations, both at low applied voltages. In order to obtain a general picture of SBD, room-temperature current-voltage (-) measurements have been performed on samples with different gate areas, oxide thicknesses, and substrate types. An astounding matching between some of these-characteristics has been found. The obtained results and the comparison with the final breakdown regime suggest that the current flow through a SBD spot is largely influenced by its atomic-scale dimensions as occurs in a point contact configuration. Experimental data are also presented which demonstrate that specific current fluctuations can be ascribed to a blocking behavior of unstable SBD conduction channels.
Intrinsic dielectric breakdown of ultra-thin gate oxides
Microelectronic Engineering, 2001
We have investigated the dynamics of intrinsic dielectric breakdown (BD) in SiO thin films of thickness in the range 2 from 35 to 3 nm. BD is obtained under constant voltage Fowler-Nordheim stress at fields between 10 and 12.5 MV/ cm. As a function of oxide thickness we have followed with high time resolution the dynamics of the BD transient and analysed the post-BD damage by using transmission electron microscopy, photon emission microscopy and measurements of the post-BD current-voltage (I-V) characteristics. Moreover, the effect of the density of electrons at the cathode on the resulting BD damage is put in evidence. The data are interpreted and discussed in the framework of a model.
Logistic modeling of progressive breakdown in ultrathin gate oxides
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003
The sigmoidal behavior exhibited by the current-time characteristics of constant voltage stressed MOS capacitors with ultrathin oxides is ascribed to a selfconstrained increase of the leakage sites population that assist the conduction process between the electrodes. To analytically describe this dynamical process we consider a classical model of population growth theories such as the Verhulst differential equation. The role played by the background tunneling current in the detection of the breakdown event is also discussed.
We have investigated the properties of soft breakdown (SBD) in thin oxide (4.5 nm) nMOSFETs with measurements of the gate and substrate leakage currents using the carrier separation technique. We have observed that, at lower gate voltages, the level of the substrate current exhibits a plateau. We propose that the observed plateau is due to the Shockley-Hall-Read (SHR) generation of hole-electron pairs in the space charge region and at the Si-SiO 2 interface. At higher voltages, the substrate current steeply increases with voltage, due to a tunneling mechanism, trap-assisted or due to a localized effective thinning of the oxide, from the substrate valence band to the gate conduction band, which becomes possible for gate voltages higher than the threshold voltage. The proposed interpretation is consistent with the results of measurements performed at different operating conditions, in the presence of light and in the case of substrate reverse bias. The presented results are also usefu...