A Review on Low Power Sram (original) (raw)

Comparison and analysis of various low power SRAM cells

Ijariit Journal

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Design and Analysis of Low Power SRAM using CMOS Technology

krishan chandra mishra

International Journal of Innovative Technology and Exploring Engineering (IJITEE), 2019

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LOW POWER SRAM DESIGNS: A REVIEW

IJESRT Journal

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A Novel Low Power Design of SRAM cell and its Performance Analysis

NISHA THANKACHAN AE

2011

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Design and Simulation Low power SRAM Circuits

IJSRD - International Journal for Scientific Research and Development

IJSRD, 2013

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Performance of Low Power SRAM Cells On SNM and Power Dissipation

Saipriya Rentachintala

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LOW POWER SRAM

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Design and analysis of low-power SRAMs

Mohammad Sharifkhani

2006

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Ijesrt International Journal of Engineering Sciences & Research Technology Low Power Sram Designs: A Review

Asifa Amin

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STUDY OF SRAM AND ITS LOW POWER TECHNIQUES

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Design and Analysis of Two Low-Power SRAM Cell Structures

Ali Afzali-Kusha

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

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IJERT-A Novel SRAM Cell Design for Low Power Applications

IJERT Journal

International Journal of Engineering Research and Technology (IJERT), 2015

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Design and Analysis of 6 T SRAM Cell with low Power Dissipation

Soumya Gadag

2012

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A LOW POWER SRAM USA GE IN FPGA MEMORY CE LL

IJESMR Journal

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Low Power SRAM Design with Reduced Read/Write Time

Shivani Yadav

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Low-Power SRAMs in Nanoscale CMOS Technologies

Kevin Zhang

IEEE Transactions on Electron Devices, 2008

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Analysis of Low Leakage Architecture of SRAM 8x1 Using Leakage Power Reduction Technique in Different Technology

sonam rathore

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An Innovative Design solution for minimizing Power Dissipation in SRAM Cell

IJERA Journal

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Ultralow-power SRAM technology

Rebecca Mih

Ibm Journal of Research and Development, 2003

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Design of a Low Power SRAM Cell by Tanner Tool 45 NM

International Journal IJRITCC

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Calculation of Power Consumption in 10 T CMOS SRAM Cell with 0.6 µm Technology Using Microwind 2 Tool

Ajita Pathak

International Journal of Innovative Research in Computer and Communication Engineering, 2015

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Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

Hooman Jarollahi

2010

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DESIGN OF AREA EFFICIENT BASED SRAM CELL USING LOW POWER

International Research Journal of Modernization in Engineering Technology and Science (IRJMETS)

International Research Journal of Modernization in Engineering Technology and Science, 2020

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STUDY OF LOW-POWER SRAM CELL AT DEEP SUB-MICRON CMOS TECHNOLOGY FOR MOBILE APPLICATIONS

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INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY AND MANAGEMENT (IJRTM), 2017

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DESIGN OF LOW POWER SRAM CELL WITH IMPROVED STABILITY

Javed Akhtar Ansari

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Comparative analysis of SRAM cell with leakage power reduction approaches

Jayanth Krishna

International Journal of Engineering & Technology, 2018

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Design and Comparison of Various Low Power nT SRAM Cells

SHILPA UNKI

2018

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A Low-Power Embedded SRAM for Wireless Applications

Wim Dehaene

IEEE Journal of Solid-State Circuits, 2007

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Implementation and Modeling of Low Power Sleepy Stack Sram

Sumeet Goyal

Journal of Advanced Sciences

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MULTI TRANSISTORS BASED SRAM FOR LOW POWER APPLICATIONS: A STUDY

IAEME Publication

IAEME PUBLICATION, 2020

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A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption using MTCMOS Technique

IOSR Journals

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Analysis of Power Dissipation & Low Power VLSI Chip Design

Editor IJMTER

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Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques

Rishabh Cn

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250nm Technology Based Low Power SRAM Memory

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Study of Speed and Leakage Power Trade-off in Various SRAM Circuits for Mobile Application

krishan chandra mishra

International Journal on Emerging Technologies (Special Issue NCETST-2017), 2017

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