A compact low power mixed-signal equalizer for gigabit Ethernet applications (original) (raw)
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A Low-Power 20-Gb/s Discrete-Time Analog Front-End for ADC-Based Serial Link Equalizers
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This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE serves two functions; linear equalization and sampling and holding for the following charge-steering ADC. The ADC uses fully differential low-power clocked comparators. Low power in the comparators is achieved by embedding a dynamic latch into the core of a charge-steering pre-amplifier. The 20-Gb/s front-end is designed and simulated in 65-nm CMOS technology. The flash ADC uses 4-stage interleaving and thus requires 4 DTLEs running at 5 Gb/s. A 5-Gb/s DTLE consumes 0.57 mW from a 1.2-V supply and the ADC consumes 15.5 mW from a 1-V supply at 20 GS/s for a total power dissipation of 17.78 mW or 0.89 pJ/bit. The ADC has an SNDR of 23.9 dB, an SFDR of 33.6 dB, and an effective number of bits (ENOB) of 3.67 bits for a sinusoidal input of frequency 9.84 ...
A general-purpose high-speed equalizer
IEEE Journal of Solid-State Circuits, 1991
The circuit presented in this paper is a high-speed selfadaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and High-Definition Multiplexed Analog Components (HD-MAC) transmission standards. It is composed of a 16-tap transversal filter and a separate operative part computing the gradient algorithm and periodically updating the filter coefficients. This 105 000-transistor chip has been designed in a CMOS 1.0-pm technology and is at this time being used in a D2-MAC reception environment.
A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet
A CMOS IC that implements the 802.3 Ethernet standards for 10-and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm 2 in a 0.6-m single-poly CMOS process and dissipates 850 mW from a 5-V supply.
A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 μm CMOS
IEEE Journal of Solid-state Circuits, 1993
Abstruct-Using a combination of architecture optimization techniques and unconventional circuit designs, a 60-MHz decision-feedback equalizer (DFE) chip is presented for high-bitrate digital modem applications. The equalizer can accommodate a wide variety of modulation formats (quaternary phase-shift keying (QPSK), 16, 64, 256 quadrature amplitude modulation (QAM)) and achieves a peak throughput rate of 480 Mb/s. The chip contains four complex-valued programmable filter taps, and also incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The transistor count is 70 000 within a 4.9-mm x 7.0-mm die area in 1.2-pm CMOS. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).
ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter
International Journal of e-Collaboration, 2020
Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this archite...
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER 10 12 was significantly increased with the use of DFE for short-to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.
Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2-p.m CMOS which can implement either an Echo Canceller or Decision-Feedback Equalizer for 2BlQ High Bit-Rate Di ital Subscriber Line (HDSL) transceivers. The 4.3 x adaptive filter which incorporates the L%S algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high bit-rate transceivers. At a 60-MHz clock rate the Echo CancellerDecision Feedback Equalizer chip can accommodate symbol rates in excess of 800 kbaud. 4.3 mm 1 , 30,000 transistor chip is a com lete self-contained
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
When operating at a gigahertz-level frequency, a high-frequency signal is distorted and degraded through the channel. To meet the demand of low cost and the low power consumption for consumer electronic products, this paper proposes a power-saving adaptive equalizer with digital-controlled self-slope detection to compensate channel losses. Reducing and shutting down high-speed circuits in addition to digitization are the most effective methods for minimizing both power and cost. This study also proposes a serial processing for reducing one high-speed detection circuit. The main concept is to use a selfslope detection circuit, which compares two continuous serial slopes, instead of a previous detection circuit, which uses a slicer. After compensation, a shutdown mechanism switches OFF the control circuit to reduce power. A serial processing enables channeling the data through the same circuit and path to avoid swing balancing and mismatch problems. An experimental chip was implemented using 90-nm 1P9M CMOS technology. In the experiment, the equalizer is operated at a supply power of 1 V with 4.35 mW. The core area occupies of 120 µm × 189 µm, and the peak-to-peak jitter measured at 5 Gb/s by using the PRBS31 pattern through a 1.5-m channel is 0.36 UI.
IEICE Electronics Express
This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65 nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unit-interval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28 Gb/s and occupies 0.023 mm 2. Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.