A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection (original) (raw)

A Low-Power 20-Gb/s Discrete-Time Analog Front-End for ADC-Based Serial Link Equalizers

arXiv: Signal Processing, 2019

This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE serves two functions; linear equalization and sampling and holding for the following charge-steering ADC. The ADC uses fully differential low-power clocked comparators. Low power in the comparators is achieved by embedding a dynamic latch into the core of a charge-steering pre-amplifier. The 20-Gb/s front-end is designed and simulated in 65-nm CMOS technology. The flash ADC uses 4-stage interleaving and thus requires 4 DTLEs running at 5 Gb/s. A 5-Gb/s DTLE consumes 0.57 mW from a 1.2-V supply and the ADC consumes 15.5 mW from a 1-V supply at 20 GS/s for a total power dissipation of 17.78 mW or 0.89 pJ/bit. The ADC has an SNDR of 23.9 dB, an SFDR of 33.6 dB, and an effective number of bits (ENOB) of 3.67 bits for a sinusoidal input of frequency 9.84 ...

A general-purpose high-speed equalizer

IEEE Journal of Solid-State Circuits, 1991

The circuit presented in this paper is a high-speed selfadaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and High-Definition Multiplexed Analog Components (HD-MAC) transmission standards. It is composed of a 16-tap transversal filter and a separate operative part computing the gradient algorithm and periodically updating the filter coefficients. This 105 000-transistor chip has been designed in a CMOS 1.0-pm technology and is at this time being used in a D2-MAC reception environment.

A pattern-guided adaptive equalizer in 65nm CMOS

2011 IEEE International Solid-State Circuits Conference, 2011

This thesis presents the design, implementation, and fabrication of a pattern-guided equalizer in a 65nm CMOS process. By counting the occurrence of 6 out of 16 4-bit patterns in the received data and utilizing their spectral content, the signal is equalized separately at f N and f N /2, where f N is half the bit rate. The design was packaged using a 64 pin Quad Flat No leads (QFN) package. Two different channels were used and the equalizer was able to open the eye for both 13dB and 17dB of attenuation at the Nyquist frequency. The adaptation performance was determined by measuring the vertical and horizontal eye openings for all possible equalizer coefficients. Measured results at 6Gb/s confirm that the adaptation engine opens a closed eye to within 2.6% of optimal vertical opening and 7% of optimal horizontal eye opening while consuming 16.8mW from a 1.2V supply.

A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 μm CMOS

IEEE Journal of Solid-state Circuits, 1993

Abstruct-Using a combination of architecture optimization techniques and unconventional circuit designs, a 60-MHz decision-feedback equalizer (DFE) chip is presented for high-bitrate digital modem applications. The equalizer can accommodate a wide variety of modulation formats (quaternary phase-shift keying (QPSK), 16, 64, 256 quadrature amplitude modulation (QAM)) and achieves a peak throughput rate of 480 Mb/s. The chip contains four complex-valued programmable filter taps, and also incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The transistor count is 70 000 within a 4.9-mm x 7.0-mm die area in 1.2-pm CMOS. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).

A compact low power mixed-signal equalizer for gigabit Ethernet applications

2006

In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 mum CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply

Design of an adaptive cable equalizer using 0.5 [mu]m [i.e. micrometer] CMOS process

2002

I would like to express my gratitude to Dr. Syed K. Islam for his relentless help and support throughout my Master's program and giving all kind of directions to finish this thesis. Many thanks to Dr. Marshall 0. Pace and Dr. M. Mostofa Howlader to be the committee members and for their suggestions. Special thanks to Dr. Benjamin J. Blalock for his generous help and valuable comments on the design phase of the project. Thanks to Mr. Barry Stakely of Transwitch Corporation, Raleigh, NC, as he introduced me to this interesting topic to research. Thanks to my group members Hasan, Hafi j, V enkatesh and Lakshmi for their continuous help and encouragement. And my parents, brothers and sisters who always keep faith on me of my success, they all deserve big thanks from me.

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

IEEE Transactions on Circuits and Systems I: Regular Papers, 2000

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain.

Design of a CMOS multi-rate adaptive continuous-time equalizer based on power spectrum estimation

International Journal of Circuit Theory and Applications, 2017

An adaptive continuous-time equalizer for reliable short-haul high-speed serial communications is described in this paper. The adaptive equalizer uses the spectrum-balancing technique to adapt its response to changes in the bandwidth, amplitude, and bit rate of the input signal. In this way, it is able to compensate the frequency response of a 1-mm diameter step-index plastic optical fiber, for lengths up to 50 m, and bit rates ranging from 400 Mb/s to 2.5 Gb/s. Experimental results are shown to demonstrate its feasibility. Copyright

An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel

2009 International Conference on Communications, Circuits and Systems, 2009

This paper presents an improved equalization circuit, with a linear equalizer (LE) and a decision feedback equalizer (DFE) in the receiver, for 10-Gb/s high-speed serial data transmission over highly lossy electrical backplane channels. Although DFE provides an effective way to compensate various channel impairments, the precursor inter-symbol interference (lSI) is still a significant problem for channel equalization. With the new equalization method, the precursor lSI is compensated with the linear equalizer, and the post-cursor lSI is cancelled by the DFE. The improved equalization circuit with programmable linear equalizer and a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of-20 dB. The results show it outperform a traditional 5-tap DFE in vertical eye-opening.