Short-channel effect and device design of extremely scaled tunnel field-effect transistors (original) (raw)
Related papers
Sub10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction
IEEE Electron Device Letters, 2011
This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.
2014
With down Scaling of MOSFET to nanometer dimensions, the OFF-state leakage current(Ioff) increases exponentially due to the non scalability of threshold voltage since the Subthreshold Swing(S) is limited to 60mV/decade. Steep Subthreshold Swing transistors based on Band to Band Tunneling (BTBT) are analyzed to improve the performance of the circuit for low power applications. This review paper discuss about various structures and modeling of Tunnel Field Effect Transistor(TFET) which replaces CMOS for greater energy efficiency which is considered to be the most critical design parameter for ubiquitous and mobile computing systems.
Source-All-Around Tunnel Field-Effect Transistor (SAA-TFET): Proposal and Design
2019
In this paper, a new source-all-around tunnel field-effect transistor (SAA-TFET) is proposed and investigated by using TCAD simulation. The tunneling junction in the SAA-TFET is divided laterally and vertically with respect to the channel direction which provides a relatively large tunneling junction area. An n+ pocket design is also introduced around the source to enhance tunneling rates and improve the device characteristics. In addition, the gate and n+ pocket region also overlap in the vertical and the lateral directions resulting in an enhanced electric field and, in turn, the ON-state current of the SAA-TFET is highly increased compared with the conventional TFET. Promising results in terms of DC (I ON , I OFF , ON/OFF current ratio and SS) and analog (cutoff frequency) performance are obtained for low (V DD = 0.5 V) and high (V DD = 1 V) supply voltages.
Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits
IEEE Transactions on Electron Devices, 2011
Improving the ON-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I ON is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I ON , a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same OFF-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.
Design of Si 0.5 Ge 0.5 based tunnel field effect transistor and its performance evaluation
Band to band tunneling (BTBT) Tunnel field effect transistor (TFET) a b s t r a c t In this work, the performance comparison of two heterojunction PIN TFETs having Si channel and Si 0.5 Ge 0.5 source with high-k (SiGe DGTFET HK) and hetero-gate dielectric (SiGe DGTFET HG) respectively with those of two homojunction Si based PIN (DGTFET HK and DGTFET HG) TFETs is performed. Similarly, by employing the technique of pocketing at source junction in above four PIN TFETs, the performances of resultant four PNPN TFETs (SiGe PNPN DGTFET HK, SiGe PNPN DGTFET HG, PNPN DGTFET HK and PNPN DGTFET HG) are also compared with each other. Due to lower tunnel resistance of SiGe based hetero-junction PIN and PNPN TFETs, the DC parameters such as ON current, ON-OFF current ratio, average subthreshold slope are improved significantly as compared to Si based PIN and PNPN TFETs respectively. The output characteristics of HG architectures in Si based homojunction PIN and PNPN TFETs is observed to be identical to with respective Si based HK PIN and PNPN TFET architectures. However, the output characteristics of HG archi-tectures in SiGe based heterojunction PIN and PNPN TFETs degrade as compared to their respective SiGe based HK PIN and PNPN TFET architectures. In ON state, SiGe based HK and HG PIN and PNPN TFETs have lower gate capacitance (C gg) as compared to their respective Si based HK and HG PIN and PNPN TFETs. Moreover, HG architecture suppresses gate to drain capacitance (C gd) and ambipolar conduction. Transconductance (g m) and cut off frequency (f T) is also observed to be higher for SiGe based PIN and PNPN TFETs.
Japanese Journal of Applied Physics, 2013
We fabricate p- and n-channel Si tunnel field-effect transistors (TFETs) with an epitaxially grown tunnel junction. In a novel source/drain-first and tunnel-junction-last fabrication process, a thin epitaxial undoped Si channel (epichannel) is deposited on a preferentially fabricated p- or n-type source area. The epichannel sandwiched by a gate insulator and a highly doped source well acts as a parallel-plate tunnel capacitor, which effectively multiplies drain current with an enlarged tunnel area. On the basis of its simple structure and easy fabrication, symmetric n- and p-transistor and complementary metal oxide semiconductor inverter operations were successfully demonstrated.
2009 IEEE International Electron Devices Meeting (IEDM), 2009
Vertical In 0.53 Ga 0.47 As tunnel field effect transistors (TFETs) with 100nm channel length and highk/metal gate stack are demonstrated with high I on /I off ratio (>10 4 ). At V DS = 0.75V, a record on-current of 20µA/µm is achieved due to higher tunneling rate in narrow tunnel gap In 0.53 Ga 0.47 As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs. Introduction: Inter-band tunnel FETs (TFETs) with a gatemodulated Zener tunnel junction at the source are of interest for MOSFET replacement since the reverse biased tunnel junction in the former eliminates the high-energy tail of the Fermi distribution of valence band electrons in the source region thereby allowing for abrupt turn-on near the OFF state 1 . However, till date, almost all Si and Si x Ge 1-x based TFETs exhibit low I on due to high tunnel barrier. We present here improved I on and I on -I off ratios utilizing a vertical In 0.53 Ga 0.47 As TFET. A fundamental advantage of the vertical transistor design is that high quality, in-situ doped junctions are realized enabling not only observation of room temperature NDR effects but also reduction of off-state reverse biased p+/i/n+ leakage. Device Fabrication: N-channel In 0.53 Ga 0.47 As TFETs were fabricated using MBE grown epitaxial structure on semiinsulating InP substrate. The epitaxial layers comprise of 300nm thick n+ drain region (Si doping of 5x10 19 cm -3 ), 100nm intrinsic channel region and 60nm thick p+ source region (C doping of 1x10 20 cm -3 ) . After source metal (Ti/Pt/Au) evaporation and lift-off, a facet dependent mesa sidewall etch is performed using citric acid and peroxide chemistry exposing the n+ region . A highly conformal 10nm thick Al 2 O 3 is deposited on the mesa sidewall using atomic layer deposition (ALD) followed by gate metallization (Pt/Au) and liftoff . A subsequent lithography step defines source/drain contact openings and the Al 2 O 3 film is removed thereof to make direct contact to the source/drain regions, followed by a final isolation etch . Figs. 1g-h show the SEM images of fabricated In 0.53 Ga 0.47 As vertical TFET featuring gate air-bridge and conformal gate stack on the sidewall. Device Results and Discussion: show the measured transfer and output characteristics of the 100nm channel length tunnel transistors at room temperature. The minimum current ("leakage floor") at V DS = 50mV is only 40 pA/µm increasing to 6nA/µm at V DS = 0.75V. The corresponding on currents are 0.5µA/µm (linear) and 20µA/µm (saturation). This translates to I on -I off ratio of ~ 10