3D integrated circuits Research Papers (original) (raw)

D stacking is a promising technology (low latency/power/area, high bandwidth); its main shortcoming is increased power density. Simultaneously, motivated by energy constraints, architectures are evolving towards greater customization, with tasks delegated to ac- celerators. Due to the widespread use of machine-learning algo- rithms and the re-emergence of neural networks (NNs) as the pre- ferred such algorithms, NN accelerators are receiving increased at- tention. They turn out to be well matched to 3D stacking: inherently 3D structures with a low power density and high across-layer band- width requirements. We present what is, to the best of our knowl- edge, the first 3D stacked NN accelerator

nterconnect is one of the main performance determinant of modern
integrated circuits
(ICs)
. The new
technology of vertical
ICs
places circuit
blocks in the vertical dimension in addition to the conventional
horizontal plane.
Compared to the planar
IC
s
, vertical
IC
s
have shorter latencies as well as lower power
consumption due to shorter wires. This also increases
speed, improves performances
and adds to
IC
s
density.
The benefits
of vertical IC
s increase as we stack more die
s
, due to successive reductions in wire
lengths.
However,
as we stack more dies, the
lattice
self
-
heating becomes
a challenging
and
critical
issue
due to the difficulty in
cooling down
the l
ayers away from the heat sink.
In this paper, we provide a
quant
itative
electro
-
thermal
analysis of the
temperatur
e rise due to stacking. M
athematical models based
on
steady state
non
-
isothermal drift
-
diffusion transport equations coupled to heat flow equation
are used
.
These
physically based models and the different heat sources in semiconductor devices will be presented
and discussed
.
Three dimensional n
umerical results did show that, compared to the planar
ICs, the
vertical ICs with 2
-
die
technology
increase the maximum temperature by 17 Kelv
in
in the die
away from
the heat sink
.
These numerical results will
also
be presented and analyzed
for a typical
2
-
die
structure of
complementary metal oxide semiconductor
(CMOS)
transistors.

This book reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. Featuring contributions from renowned experts in their respective fields, this comprehensive reference provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.