Wirless NoC Research Papers - Academia.edu (original) (raw)
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Recent papers in Wirless NoC
One of the key challenges in designing a quality of service (QOS) scheme for IEEE 802.11 wireless LANs (WLANS) is reducing collisions and improving throughput. Existed Adaptive contention windows mechanisms can reduce collisions of all... more
One of the key challenges in designing a quality of service (QOS) scheme for IEEE 802.11 wireless LANs (WLANS) is reducing collisions and improving throughput. Existed Adaptive contention windows mechanisms can reduce collisions of all traffic. However, adaptive contention window algorithms cannot guarantee the absolute priority of the high-priority traffic. Especially in the heavy loading, low-priority traffics will introduce unnecessary collisions and cause unsuccessful transmission. Our scheme aims to share the transmission channel efficiently and to provide the absolute differentiated traffic scheme. Relative priorities are provisioned by adjusting the range of the back-off timer of low-priority traffic class taking into account both applications requirements and network conditions. We demonstrate the effectiveness of our solution by comparing with existing approaches through extensive simulations. Results show that our scheme reduces frame delay as well when traffic load is heavy. Furthermore, our scheme is simple and easy to implement.
The HITS and PageRank algorithms and K-Means clustering algorithm are two main methods for detecting spam machines. In PageRank algorithm, it is proposed to calculate weights based on different factors. Correct selection of weights has... more
The HITS and PageRank algorithms and K-Means clustering algorithm are two main methods for detecting spam machines. In PageRank algorithm, it is proposed to calculate weights based on different factors. Correct selection of weights has important role in the accuracy of the algorithm. In this paper, we propose a good method for convenient selection of weights. We first executed the K-Means algorithm on the traffic of a big target network and divided IP addresses to two parties, normal and anomalous, and assigned a weight to the IP addresses of anomalous party which is used in calculating the energy rank of the second method. With executing the second algorithm, we found a larger set of IP addresses of spam machines and found that we have increased the accuracy of the algorithms perceptibly.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We present TriBASim in this paper, a NoC... more
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the
core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We
present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are
connected in recursive triplets .TriBA network topology performance analysis have been carried out from
different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks
a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture
based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a
simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by
giving them something to just plug in desired parameters and have nodes and topology set up ready for
analysis.
Interconnect fabric requires easy integration of computational block operating with unrelated clocks. This paper presents asynchronous interconnect with ternary tree asynchronous network for Globally Asynchronous Locally Synchronous... more
Interconnect fabric requires easy integration of computational block operating with unrelated clocks. This paper presents asynchronous interconnect with ternary tree asynchronous network for Globally Asynchronous Locally Synchronous (GALS) system-on-chip (SOC). Here architecture is proposed for interconnection with ternary tree asynchronous network where ratio of number NOC design unit and number of router is 4:1,6:2, 8:3,10:4 etc .It is scalable for any number of NOC design unit. It offers an easy integration of different clock domain with low communication overhead .NOC design unit for GALS 'SOC is formulated by wrapping synchronous module with input port along with input port controller, output port along with output port controller and local clock generator. It creates the interface between synchronous to asynchronous and asynchronous to synchronous. For this purpose four port asynchronous routers is designed with routing element and output arbitration and buffering with micro-pipeline. This interconnect fabric minimizes silicon area, minimize Latency and maximize throughput. Here functional model is made for TTAN and application MPEG4 is mapped on the Network .Desired traffic pattern is generated and performance of the network is evaluated. Significant improvement in the network performance parameter has been observed.
This study proposes a new router architecture to improve the performance of dynamic allocation of virtual channels. The proposed router is designed to reduce the hardware complexity and to improve power and area consumption,... more
This study proposes a new router architecture to improve the performance of dynamic allocation of virtual channels. The proposed router is designed to reduce the hardware complexity and to improve power and area consumption, simultaneously. In the new structure of the proposed router, all of the controlling components have been implemented sequentially inside the allocator router modules. This optimizes communications between the controlling components and eliminates the most of hardware overloads of modular communications. Eliminating additional communications also reduces the hardware complexity. In order to show the validity of the proposed design in real hardware resources, the proposed router has been implemented onto a Field-Programmable Gate Array (FPGA). Since the implementation of a Network-on-Chip (NoC) requires certain amount of area on the chip, the suggested approach is also able to reduce the demand of hardware resources. In this method, the internal memory of the FPGA is used for implementing control units. This memory is faster and can be used with specific patterns. The use of the FPGA memory saves the hardware resources and allows the implementation of NoC based FPGA.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We present TriBASim in this paper, a NoC... more
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are connected in recursive triplets .TriBA network topology performance analysis have been carried out from different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by giving them something to just plug in desired parameters and have nodes and topology set up ready for analysis.