Paging (original) (raw)

Last Updated : 6 Apr, 2026

Paging is a memory management technique in which a process is divided into fixed-size blocks called pages, and physical memory is divided into frames of the same size. Pages are loaded from secondary storage into main memory as needed.

Page_tABLE

Paging in Operating System

To keep track of where each page is stored in memory, the operating system uses a page table. This table shows the connection between the logical page numbers and the physical page frames (actual locations in RAM).

**Note: The memory management unit uses the page table to convert logical addresses into physical addresses, so the program can access the correct data in memory.

Paging in Memory Management

Paging addresses common challenges in allocating and managing memory efficiently. Why paging is needed as a Memory Management technique:

Terminologies Associated with Memory Control

Important Features of Paging

Working of Paging

When a process requests memory, the operating system allocates one or more page frames to the process and maps the process's logical pages to the physical page frames. When a program runs, its pages are loaded into any available frames in the physical memory.

paging

Working of Paging

Each program has a page table, which the operating system uses to keep track of where each page is stored in physical memory. When a program accesses data, the system uses this table to convert the program's address into a physical memory address.

**Steps Involved in Paging :

If Logical Address Space = 128 M words = 128 × 220 = 27 × 220 = 227 words
Then Logical Address = log2(227)= **27 bits

If Physical Address Space = 16 M words = 16 × 220 = 24 × 220 = 224 words
Then Physical Address = log2(224)= **24 bits

The mapping from virtual to physical address is done by the Memory Management Unit (MMU) which is a hardware device and this mapping is known as the paging technique.

Example

**Number of frames = Physical Address Space / Frame Size = 4K / 1K = 4 = 22
**Number of Pages = Logical Address Space / Page Size = 8K / 1K = 23

**The address generated by the CPU is divided into:

  1. **Page number(p): Number of bits required to represent the pages in Logical Address Space or Page number
  2. **Page offset(d): Number of bits required to represent a particular word in a page or page size of Logical Address Space or word number of a page or page offset.

**A Physical Address is divided into two main parts:

  1. **Frame Number(f): Number of bits required to represent the frame of Physical Address Space or Frame number frame
  2. **Frame Offset(d): Number of bits required to represent a particular word in a frame or frame size of Physical Address Space or word number of a frame or frame offset.

**Physical Address = (Frame Number << Number of Bits in Frame Offset) + Frame Offset
where "<<" represents a bitwise left shift operation.

Hardware implementation of Paging

The hardware implementation of the page table can be done by using dedicated registers. But the usage of the register for the page table is satisfactory only if the page table is small. If the page table contains a large number of entries then we can use TLB(translation Look-aside buffer), a special, small, fast look-up hardware cache.

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Page Table with TLB

**Main memory access time = m, If page table are kept in main memory, Effective access time = m(for page table) + m(for particular page in page table)

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