Multiport Selector - Distribute arbitrary subsets of input rows or columns to multiple output

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Distribute arbitrary subsets of input rows or columns to multiple output ports

Libraries:
DSP System Toolbox / Signal Management / Indexing
DSP System Toolbox HDL Support / Signal Management

Description

The Multiport Selector block extracts multiple subsets of rows or columns from M_-by-N input matrix_u, and propagates each new submatrix to a distinct output port. For more details, see the description of the Select andIndices to output parameters.

Examples

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Multichannel signals, represented by matrices in the Simulink® environment, are frequently used in signal processing models for efficiency and compactness. Though most of the signal processing blocks can process multichannel signals, you may need to access just one channel or a particular range of samples in a multichannel signal. You can access individual channels of the multichannel signal by using the blocks in the Indexing library. This library includes the Selector, Submatrix, Variable Selector, Multiport Selector, and Submatrix blocks.

You can split a multichannel based signal into single-channel signals using the Multiport Selector block. This block allows you to select specific rows and/or columns and propagate the selection to a chosen output port. In this example, a three-channel signal of size 3-by-1 is deconstructed into three independent signals of sample period 1 second.

Open the ex_splitmltichsbsigsind model.

Double-click the Signal From Workspace block, and set the block parameters as follows:

Based on these parameters, the Signal From Workspace block outputs a three-channel signal with a sample period of 1 second.

Save these parameters and close the dialog box by clicking OK.

Double-click the Multiport Selector block. Set the block parameters as follows, and then click OK:

Based on these parameters, the Multiport Selector block extracts the rows of the input. The Indices to output parameter setting specifies that row 1 of the input should be reproduced at output 1, row 2 of the input should be reproduced at output 2, and row 3 of the input should be reproduced at output 3.

Run the model.

At the MATLAB® command line, type dsp_examples_yout. Because the input signal is random, your output might be different than the output shown here. This signal is the first row of the input to the Multiport Selector block. You can view the other two input rows by typing dsp_examples_yout1 and dsp_examples_yout2, respectively.

dsp_examples_yout(:,:,1) =

0.8884

dsp_examples_yout(:,:,2) =

-0.8095

dsp_examples_yout(:,:,3) =

0.3252

dsp_examples_yout(:,:,4) =

-1.7115

dsp_examples_yout(:,:,5) =

0.3192

dsp_examples_yout(:,:,6) =

-0.0301

dsp_examples_yout(:,:,7) =

1.0933

dsp_examples_yout(:,:,8) =

0.0774

dsp_examples_yout(:,:,9) =

-0.0068

dsp_examples_yout(:,:,10) =

0.3714

dsp_examples_yout(:,:,11) =

 0

You have now successfully created three single-channel signals from a multichannel signal using a Multiport Selector block.

Ports

Input

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Specify the input u as a vector or a matrix of size_M_-by-N. The block treats an unoriented length-M vector input as an_M_-by-1 matrix.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated

Output

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Row- or column-subsets of input, propagated to each output port. Each cell in the Indices to output array determines the subset of input rows or columns to be propagated to the respective output port. The total number of cells in the Indices to output array determines the number of output ports on the block.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated

Parameters

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Select the input dimension as:

A given input row or column can appear any number of times in any of the outputs, or not at all.

When an index references a nonexistent row or column of the input, the block reacts with the action you specify using the Invalid index parameter.

Specify the row- or column-subsets to propagate to each of the output ports as a cell array. The _k_th cell contains a one-dimensional indexing expression specifying the subset of input rows or columns to be propagated to the _k_th output port. The total number of cells in the array determines the number of output ports on the block.

Consider the following Indices to output cell array. This is a four-cell array which requires the block to generate four independent outputs (each at a distinct port).

{4,[1:2 5],[7;8],10:-1:6}

The following table shows the dimensions of these outputs whenSelect = Rows and the input dimension is _M_-by-N.

Cell Expression Description Output Size
1 4 Row 4 of input 1-by-N
2 [1:2 5] Rows 1, 2, and 5 of input 3-by-N
3 [7;8] Rows 7 and 8 of input 2-by-N
4 10:-1:6 Rows 10, 9, 8, 7, and 6 of input 5-by-N

Specify the action to take when there is an invalid index value. You can select one of the following options:

Block Characteristics

Data Types Boolean | double enumerated fixed point integer single
Direct Feedthrough no
Multidimensional Signals no
Variable-Size Signals no
Zero-Crossing Detection no

Extended Capabilities

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Generated code relies on the memcpy ormemset function (string.h) under certain conditions.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline (HDL Coder).
OutputPipeline Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced before R2006a