Processor-in-the-Loop Simulation - MATLAB & Simulink (original) (raw)
Test generated code on target processor or simulator
A processor-in-the-loop (PIL) simulation cross-compiles generated source code, and then downloads and runs object code on your target hardware. By comparing normal and PIL simulation results, you can test the numerical equivalence of your model and the generated code. During a PIL simulation, you can collect code coverage and execution-time metrics for the generated code.
A PIL simulation requires a connectivity configuration.
Apps
| SIL/PIL Manager | Verify generated code |
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Namespaces
| target | Manage target hardware and build tool information |
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Classes
| target.AddOn | Describe add-on properties for target type (Since R2020b) |
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| target.API | Describe API details (Since R2020b) |
| target.APIImplementation | Describe API implementation details (Since R2020b) |
| target.Board | Provide hardware board details (Since R2020b) |
| target.BuildDependencies | Describe C and C++ build dependencies to associate with target hardware (Since R2020b) |
| target.CommunicationChannel | Describe communication channel properties (Since R2020b) |
| target.CommunicationInterface | Describe data I/O details for target hardware (Since R2020b) |
| target.CommunicationProtocolStack | Describe communication protocol parameters (Since R2020b) |
| target.Connection | Base class for target connection properties (Since R2020b) |
| target.ConnectionProperties | Describe target-specific connection properties (Since R2020b) |
| target.MainFunction | Provide C and C++ dependencies for main function of target hardware application (Since R2020b) |
| target.PILProtocol | Describe PIL protocol implementation for target hardware (Since R2020b) |
| target.Port | Describe connection via target hardware port (Since R2021a) |
| target.PortConnection | Describe target connection port (Since R2020b) |
| target.Processor | Provide target processor information |
| target.RS232Channel | Describe serial communication channel (Since R2020b) |
| target.TargetConnection | Provide details about connecting MATLAB computer to target hardware (Since R2020b) |
| target.TCPChannel | Describe TCP communication properties (Since R2020b) |
| target.Tools | Describe properties of tools for target hardware (Since R2020b) |
| target.UDPChannel | Describe UDP communication (Since R2020b) |
| target.ApplicationStatus | Describe status of application on target hardware (Since R2021a) |
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| target.Breakpoint | Provide breakpoint details for debugger (Since R2021a) |
| target.DebugExecutionTool | Provide MATLAB service interface for debugger to manage processes on target hardware (Since R2023a) |
| target.DebugIOTool | Debug byte stream I/O tool service interface (Since R2021a) |
| target.ExecutionService | Describe implementation of execution service for target application (Since R2021a) |
| target.ExecutionTool | MATLAB service interface for tool that manages application execution on target hardware (Since R2021a) |
| target.MATLABDependencies | Describe MATLAB class and function dependencies (Since R2021a) |
| target.ApplicationExecutionTool | Capture system command information to run application from MATLAB computer (Since R2020b) |
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| target.Command | Capture system command for execution on MATLAB computer (Since R2020b) |
| target.HostProcessExecutionTool | Capture system command information to run target application from MATLAB computer (Since R2020b) |
| target.SystemCommandExecutionTool | Capture system command information to run target application from MATLAB computer (Since R2020b) |
| target.Function | Provide function signature information (Since R2020b) |
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| target.Timer | Provide timer details for processor (Since R2020b) |
Objects
| rtw.connectivity.ComponentArgs | Provide parameters for each target connectivity component |
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| rtw.connectivity.Config | Define connectivity implementation that comprises builder, launcher, and communicator components |
| rtw.connectivity.ConfigRegistry | Register connectivity configuration |
| rtw.connectivity.MakefileBuilder | Configure toolchain-based build process |
| rtw.connectivity.Launcher | Control downloading, starting, and resetting of a target application |
| rtw.connectivity.RtIOStreamHostCommunicator | Configure development computer communications with target processor |
| rtw.pil.RtIOStreamApplicationFramework | Configure target-side communications |
Functions
| rtIOStreamClose | Shut down communications channel |
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| rtIOStreamOpen | Initialize communications channel |
| rtIOStreamRecv | Receive data through communication channel |
| rtIOStreamSend | Send data through communication channel |
| rtiostreamtest | Test custom rtiostream interface implementation |
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| rtiostream_wrapper | Test rtiostream shared library functions in MATLAB |
| piltest | Verify custom target connectivity configuration for Simulink PIL simulation |
Topics
- SIL and PIL Simulations
An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL). - Choose a SIL or PIL Approach
Test code generated from top models, referenced models, or subsystems. - Create PIL Target Connectivity Configuration for Simulink
Customize PIL simulation for your target environment. - Host-Target Communication for Simulink PIL Simulation
Use thertiostreamAPI for communication between your development computer and target hardware during a PIL simulation. - Specify Hardware Timer for Simulink
Specify a hardware timer using the Code Replacement Tool. - Set Up PIL Connectivity by Using Target Framework
Provide PIL connectivity between Simulink® and the target hardware. - Custom Toolchain Directives Required for Code Coverage and Execution Profiling
Specify compiler directives for building PIL application that supports code coverage analysis and execution profiling. - Configure and Run PIL Simulation
Set up and run top-model PIL, Model block PIL, and PIL block simulations. - Unit Test Subsystem Code with SIL/PIL Manager
Perform unit testing on atomic subsystem by using SIL/PIL Manager. - SIL/PIL Manager Verification Workflow
A simplified workflow for verifying generated code. - PIL Simulation Sequence
How a PIL simulation proceeds. - Simulation Mode Override Behavior in Model Reference Hierarchy
How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy. - Field-Oriented Control of Permanent Magnet Synchronous Machine
Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times. - Security for PIL Simulations
Security measures for PIL simulations. - SIL and PIL Limitations
Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.
Troubleshooting
Debug Generated Code During SIL or PIL Simulation
Use a debugger to understand the behavior of generated code.
View SIL and PIL Files in Code Generation Report
Produce a code generation report and static code metrics that cover SIL and PIL files.
Verification of Code Generation Assumptions
The SIL or PIL simulation checks code generation assumptions.
Featured Examples
Test Generated Code with SIL and PIL Simulations
Use software-in-the-loop (SIL) and processor-in-the-loop (PIL) simulations to test numerical equivalence between model components and generated code.
Configure Processor-In-The-Loop (PIL) for a Custom Target
Create target connectivity configuration and run PIL simulation.
Create a Target Communication Channel for Processor-in-the-Loop (PIL) Simulation
Use rtiostream interface to provide a communication channel for PIL simulations.