Automatic Iterative Optimization - MATLAB & Simulink (original) (raw)

Automatic iterative optimization enables you to optimize your clock frequency without specifying individual optimization options, such as input or output pipelining, distributed pipelining, or loop unrolling. Clock frequency is determined by the critical path of your design. Automatic iterative optimization improves clock frequency by inserting pipeline registers to break and shorten the critical path.

You can use hdlcoder.optimizeDesign to optimize your clock frequency in these ways:

How Automatic Iterative Optimization Works

You can specify your clock frequency goal, the maximum number of iterations, and the timing strategy for the iterative optimization by using thehdlcoder.OptimizationConfig object properties. Depending on the timing strategy that you choose, synthesis (the default) or critical path estimation, the steps that HDL Coder performs for each iteration vary.

Running the automatic iterative optimization with synthesis can take a long time, depending on the complexity of your design. For example, when running thehdl.optimizeDesign function that has synthesis as the timing strategy, synthesis can occupy nearly 94% of the run time of this function. To help mitigate the runtime and still use synthesis, thehdlcoder.optimizeDesign function can regenerate code from a previous run or resume from an interrupted run.

To help mitigate the runtime most effectively, you can choose critical path estimation as your timing strategy. Critical path estimation provides an estimated critical path rather than the actual critical path determined by synthesis. When using critical path estimation, automatic iterative optimization avoids model generation and HDL code generation to help increase the speed of every iteration. Critical path estimation as the timing strategy is most effective for placement of delays and reducing the critical path when you generate a timing database for your target device by first using the genhdltdb function. For an example that runs thehdlcoder.optimizeDesign function using both strategies, seeUse Critical Path Estimation for Faster Optimization.

If you choose critical path estimation as your timing strategy, the automatic iterative optimization performs these steps:

  1. Analyzes the logic in your design.
  2. Estimates the critical path, and obtains timing analysis data by using a timing database. For more information, see Critical Path Estimation Without Running Synthesis.
  3. Inserts pipeline registers to break the critical path.
  4. Balances delays.
  5. Saves iteration data in a new folder.

If you choose synthesis as your timing strategy, the automatic iterative optimization performs these steps:

  1. Analyzes the logic in your design.
  2. Generates code.
  3. Uses the synthesis tool to analyze the generated code and obtains post-map timing analysis data.
  4. Back-annotates the design by using the timing analysis data.
  5. Inserts pipeline registers to break the critical path.
  6. Balances delays.
  7. Saves iteration data in a new folder.

When HDL Coder has met your clock frequency goal or it has reached the maximum number of iterations, it saves the generated code and iteration data in a new folder and generates a report that describes the final critical path.

Automatic Iterative Optimization Output

When HDL Coder exits the optimization loop, it saves the results of the final iteration in a folder,hdlsrc/_`yourmodelname`_/hdlexpl/Final-_`timestamp`_.

The final iteration folder contains:

Automatic Iterative Optimization Report

HDL Coder generates a report for the final optimization iteration and saves it in the final iteration folder,hdlsrc/_`yourmodelname`_/hdlexpl/Final-_`timestamp`_.

The final optimization report, summary.html, contains:

Automatic Iterative Optimization Synthesis Tool and Hardware

If you are using synthesis as the timing strategy, your synthesis tool must be Xilinx® ISE or Xilinx Vivado®. Your target device must be a Xilinx FPGA.

Limitations of Automatic Iterative Optimization

See Also

hdlcoder.optimizeDesign | hdlcoder.OptimizationConfig