launchVCS - Start and configure Synopsys

  VCS simulator for use with HDL Verifier software - MATLAB ([original](https://in.mathworks.com/help/hdlverifier/ref/launchvcs.html)) ([raw](?raw))

Start and configure Synopsys VCS simulator for use with HDL Verifier software

Since R2024b

Syntax

Description

launchVCS([VerilogFiles](#mw%5F416e959f-93af-4447-b23b-1184a855915c)=files,[HDLTopLevelName](#mw%5F8a99c04a-22cc-4a4e-996e-e3475d34c14b)=topModule); performs these actions:

The scripts set up the GCC environment and load the correct HDL Verifier™ library into the Synopsys® VCS simulator.

To generate custom scripts, use launchVCS to generate a shell script template (.sh). Then, perform one of the following actions:

In batch mode, the function returns only after launching and starting the HDL simulator. In interactive mode, the function returns without waiting for the HDL simulator to start.

example

launchVCS([VHDLFiles](#mw%5F445a2462-3c54-43e4-82ea-fdd90fc74c9f)=files,[HDLTopLevelName](#mw%5F8a99c04a-22cc-4a4e-996e-e3475d34c14b)=topModule); generates HDL compilation scripts and simulation launch scripts, then compiles the VHDL® files and starts the VCS simulator.

example

launchVCS([VerilogFiles](#mw%5F416e959f-93af-4447-b23b-1184a855915c)=files,[VHDLFiles](#mw%5F445a2462-3c54-43e4-82ea-fdd90fc74c9f)=files,[HDLTopLevelName](#mw%5F8a99c04a-22cc-4a4e-996e-e3475d34c14b)=topModule); generates HDL compilation scripts and simulation launch scripts for a mixed-language design. Then, the function compiles the HDL files and starts the VCS simulator.

launchVCS(__,[Name=Value](#namevaluepairarguments)); specifies options using one or more name-value arguments in addition to the input arguments in previous syntaxes.

Examples

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Compile and launch a single-file Verilog design for cosimulation with Simulink®. Then, launch Synopsys VCS.

launchVCS( ... VerilogFiles="myinverter.v", ... HDLTopLevelName="myinverter" ... );

Compile and launch a VHDL design in batch mode.

In batch mode, the VCS simulator exits after the simulation completes. Relaunch the simulation by calling launchVCS again with theSkipScriptGeneration and SkipCompilation arguments.

coreLaunchArgs={"VHDLFiles",["foo1.vhd","foo2.vhd"],"HDLTopLevelName","top","RunMode","batch" };

launchVCS(... coreLaunchArgs{:},... "SkipScriptGeneration", true,... "SkipCompilation", true... );

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, whereName is the argument name and Value is the corresponding value.

Example: launchVCS(VerilogFiles="myinverter.v",HDLTopLevelName="myinverter");

You must specify HDLTopLevelName, and VerilogFiles or VHDLFiles. Specify both for a mixed language design.

Cosimulation link type, specified as a string. Select between:

Data Types: string

Location of the Verilog files, specified as a string or string array of file names. Specify the location as a full path, or relative to the RunDirectory location.

Data Types: string

Location of the VHDL files, specified as a string or as a string array of file names. Specify the location as a full path, or relative to the RunDirectory location.

Data Types: string

Name of the HDL top-level module, specified as a string scalar.

Data Types: string

Location to run the HDL simulator, specified as a folder path.

The following conditions apply to this argument:

Data Types: string | char

Run mode for the HDL simulator, specified as the comma-separated pair consisting of 'RunMode' and one of the following values:

Flags which are specific for vlogan – the VCS Verilog analysis stage, specified as a string.

Data Types: string

Flags which are specific for vhdlan – the VCS VHDL analysis stage, specified as a string.

Data Types: string

Path to the signal access file, specified as a string. The files specifies which signals have read/write/force access to the cosimulation application. See your Synopsys VCS documentation on how to create this file.

vcs compilation and elaboration flags.

Tcl commands to execute before starting the HDL simulation. For example, you can specify simple waveform generation statements for signals such as clocks, resets, and enables.

Example: PreSimulationTcl=["force UDelay.clk 1 0, 0 5 -repeat 10","force UDelay.reset 1 0, 0 5"]

Tcl commands to execute after finishing the HDL simulation.

Specify the number of seconds to wait for the HDL simulator to start before reporting an error. To avoid waiting for the simulator to start, use the value0.

Dependencies

This argument is valid only when you set RunMode tobatch or batch-with-terminal.

String array of HDL Cosimulation block instances to use in cosimulation.

When you do not specify this argument, all cosimulation blocks in current model are used.

Dependencies

This argument is for Simulink cosimulation only.

Specify the communications mechanism between Simulink and VCS:

Dependencies

The value block-property is available for Simulink cosimulation only.

String array of environment variables for use by the compilation and launch scripts. Specify as VAR=value, where VAR is the variable name, and value is the assigned value.

When set to true, the function prevents generation of compilation, launch, pre-simulation, and post-simulation TCL scripts.

Data Types: logic

Do not execute the compilation script.

Data Types: logic

Do not execute the launch script.

Data Types: logic

Path to the HDL Verifier HDL libraries. If you do not specify this argument, the function uses the default path in the MATLAB installation.

Specify the version of GCC to use:

Path to nondefault VG_GNU_PACKAGE, specified as a string. You must specify this argument to compile your files when:

Dependencies

The GCCVersion argument must be set tovg-gnu-gcc-9.5.0.

Version History

Introduced in R2024b

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You can now cosimulate Synopsys VCS simulator with a MATLAB function or System object. Set the LinkType argument to MATLAB or MATLAB System Object.