[llvm-dev] [RFC] Vector Predication (original) (raw)

Jacob Lifshay via llvm-dev llvm-dev at lists.llvm.org
Fri Feb 1 02:10:36 PST 2019

On Fri, Feb 1, 2019 at 1:54 AM Simon Moll <moll at cs.uni-saarland.de> wrote:

Hi, On 1/31/19 11:20 PM, Jacob Lifshay wrote:

We're in-progress designing a RISC-V extension ( http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4): <VL x <4 x float>> where each predicate bit masks out a whole short vector. We're using this extension to vectorize graphics code where where variables in the pre-vectorization code are short vectors. So, vectorizing code like: for(int i = 0; i < 1000; i++)_ _{_ _vec4 color = colors[i];_ _vec3 normal = normals[i];_ _color.rgb *= fmax(0.0, dot(normal, lightdir));_ _colors[i] = color;_ _}_ _I'm planning on passing already vectorized code into LLVM and using LLVM_ _as a backend for optimization and JIT code generation._ _Do you think the EVL proposal would support an ISA like this as it's_ _currently written (by pattern matching on predicate expansion and_ _vector-length multiplication)?_ _Or, do you think the EVL proposal would need modification to effectively_ _support this (by adding a element group size argument to EVL intrinsics or_ _something)?_ _We could untie the mask length from the data length:_ _%result = call <scalable 4 x float> @llvm.evl.fsub.v4f32(<scalable 4 x_ _float> %x, <scalable 4 x float> %y, <scalable 1 x i1> %M, i32 %L) would then indicate the the mask %M applies to groups of "4 / 1" float elements. Sounds good to me. I haven't checked if the current code allows for that.

Jacob -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190201/4a503f3d/attachment.html>

More information about the llvm-dev mailing list