AArch64AddressingModes.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H

14#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H

21#include

23namespace llvm {

53 switch (ST) {

68 }

69 return nullptr;

70}

74 switch ((Imm >> 6) & 0x7) {

81 }

82}

86 return Imm & 0x3f;

87}

99 unsigned Imm) {

100 assert((Imm & 0x3f) == Imm && "Illegal shifted immediate value!");

101 unsigned STEnc = 0;

102 switch (ST) {

109 }

110 return (STEnc << 6) | (Imm & 0x3f);

111}

112

113

114

115

116

117

119 return Imm & 0x7;

120}

121

122

124 assert((Imm & 0x7) == Imm && "invalid immediate!");

125 switch (Imm) {

135 }

136}

137

141

142

143

144

145

146

147

148

149

150

152 switch (ET) {

162 }

163}

164

165

166

167

168

169

171 unsigned Imm) {

172 assert((Imm & 0x7) == Imm && "Illegal shifted immediate value!");

174}

175

176

177

179 return (Imm & 0x1) != 0;

180}

181

182

183

187

188

189

190

191

192

193

194

195

196

197

198

199

204

206 return ((elt & 1) << (size-1)) | (elt >> 1);

207}

208

209

210

211

212

215 if (Imm == 0ULL || Imm == ~0ULL ||

217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))

218 return false;

219

220

222

223 do {

226

227 if ((Imm & Mask) != ((Imm >> Size) & Mask)) {

229 break;

230 }

231 } while (Size > 2);

232

233

236 Imm &= Mask;

237

240 assert(I < 64 && "undefined behavior");

242 } else {

243 Imm |= ~Mask;

245 return false;

246

248 I = 64 - CLO;

250 }

251

252

253

254

255 assert(Size > I && "I should be smaller than element size");

256 unsigned Immr = (Size - I) & (Size - 1);

257

258

259

261

262

263

264 NImms |= (CTO-1);

265

266

267 unsigned N = ((NImms >> 6) & 1) ^ 1;

268

269 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);

270 return true;

271}

272

273

274

279

280

281

285 assert(res && "invalid logical immediate");

286 (void)res;

287 return encoding;

288}

289

290

291

292

294

295 unsigned N = (val >> 12) & 1;

296 unsigned immr = (val >> 6) & 0x3f;

297 unsigned imms = val & 0x3f;

298

299 assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");

301 assert(len >= 0 && "undefined logical immediate encoding");

302 unsigned size = (1 << len);

303 unsigned R = immr & (size - 1);

304 unsigned S = imms & (size - 1);

305 assert(S != size - 1 && "undefined logical immediate encoding");

306 uint64_t pattern = (1ULL << (S + 1)) - 1;

307 for (unsigned i = 0; i < R; ++i)

308 pattern = ror(pattern, size);

309

310

311 while (size != regSize) {

312 pattern |= (pattern << size);

314 }

315 return pattern;

316}

317

318

319

320

322 unsigned regSize) {

323

324 unsigned N = (val >> 12) & 1;

325 unsigned imms = val & 0x3f;

326

327 if (regSize == 32 && N != 0)

328 return false;

330 if (len < 0)

331 return false;

332 unsigned size = (1 << len);

333 unsigned S = imms & (size - 1);

334 if (S == size - 1)

335 return false;

336

337 return true;

338}

339

340

341

342

344

345

346 uint8_t Sign = (Imm >> 7) & 0x1;

347 uint8_t Exp = (Imm >> 4) & 0x7;

348 uint8_t Mantissa = Imm & 0xf;

349

350

351

352

353

354

356 I |= Sign << 31;

357 I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;

358 I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;

359 I |= (Exp & 0x3) << 23;

360 I |= Mantissa << 19;

362}

363

364

365

366

368 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;

369 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15;

370 int32_t Mantissa = Imm.getZExtValue() & 0x3ff;

371

372

373

374 if (Mantissa & 0x3f)

375 return -1;

376 Mantissa >>= 6;

377

378

379 if (Exp < -3 || Exp > 4)

380 return -1;

381 Exp = ((Exp+3) & 0x7) ^ 4;

382

383 return ((int)Sign << 7) | (Exp << 4) | Mantissa;

384}

385

389

390

391

392

394 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;

395 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127;

396 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff;

397

398

399

400 if (Mantissa & 0x7ffff)

401 return -1;

402 Mantissa >>= 19;

403 if ((Mantissa & 0xf) != Mantissa)

404 return -1;

405

406

407 if (Exp < -3 || Exp > 4)

408 return -1;

409 Exp = ((Exp+3) & 0x7) ^ 4;

410

411 return ((int)Sign << 7) | (Exp << 4) | Mantissa;

412}

413

417

418

419

420

422 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;

423 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023;

424 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;

425

426

427

428 if (Mantissa & 0xffffffffffffULL)

429 return -1;

430 Mantissa >>= 48;

431 if ((Mantissa & 0xf) != Mantissa)

432 return -1;

433

434

435 if (Exp < -3 || Exp > 4)

436 return -1;

437 Exp = ((Exp+3) & 0x7) ^ 4;

438

439 return ((int)Sign << 7) | (Exp << 4) | Mantissa;

440}

441

445

446

447

448

449

450

452 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

453 ((Imm & 0xffffff00ffffff00ULL) == 0);

454}

455

457 return (Imm & 0xffULL);

458}

459

462 return (EncVal << 32) | EncVal;

463}

464

465

467 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

468 ((Imm & 0xffff00ffffff00ffULL) == 0);

469}

470

472 return (Imm & 0xff00ULL) >> 8;

473}

474

477 return (EncVal << 40) | (EncVal << 8);

478}

479

480

482 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

483 ((Imm & 0xff00ffffff00ffffULL) == 0);

484}

485

487 return (Imm & 0xff0000ULL) >> 16;

488}

489

492 return (EncVal << 48) | (EncVal << 16);

493}

494

495

497 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

498 ((Imm & 0x00ffffff00ffffffULL) == 0);

499}

500

502 return (Imm & 0xff000000ULL) >> 24;

503}

504

507 return (EncVal << 56) | (EncVal << 24);

508}

509

510

512 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

513 (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&

514 ((Imm & 0xff00ff00ff00ff00ULL) == 0);

515}

516

518 return (Imm & 0xffULL);

519}

520

523 return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;

524}

525

526

528 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

529 (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&

530 ((Imm & 0x00ff00ff00ff00ffULL) == 0);

531}

532

534 return (Imm & 0xff00ULL) >> 8;

535}

536

539 return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);

540}

541

542

544 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

545 ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);

546}

547

549 return (Imm & 0xff00ULL) >> 8;

550}

551

554 return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;

555}

556

557

559 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

560 ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);

561}

562

565 return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;

566}

567

569 return (Imm & 0x00ff0000ULL) >> 16;

570}

571

572

574 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

575 ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&

576 ((Imm >> 56) == (Imm & 0x000000ffULL));

577}

578

580 return (Imm & 0xffULL);

581}

582

585 EncVal |= (EncVal << 8);

586 EncVal |= (EncVal << 16);

587 EncVal |= (EncVal << 32);

588 return EncVal;

589}

590

591

592

594#if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \

595 defined(_M_ARM64)

596

597

598

599

600 constexpr uint64_t Mask = 0xFFULL;

601 uint64_t ByteA = (Imm >> 56) & Mask;

602 uint64_t ByteB = (Imm >> 48) & Mask;

603 uint64_t ByteC = (Imm >> 40) & Mask;

604 uint64_t ByteD = (Imm >> 32) & Mask;

605 uint64_t ByteE = (Imm >> 24) & Mask;

606 uint64_t ByteF = (Imm >> 16) & Mask;

607 uint64_t ByteG = (Imm >> 8) & Mask;

609

610 return (ByteA == 0ULL || ByteA == Mask) && (ByteB == 0ULL || ByteB == Mask) &&

611 (ByteC == 0ULL || ByteC == Mask) && (ByteD == 0ULL || ByteD == Mask) &&

612 (ByteE == 0ULL || ByteE == Mask) && (ByteF == 0ULL || ByteF == Mask) &&

613 (ByteG == 0ULL || ByteG == Mask) && (ByteH == 0ULL || ByteH == Mask);

614#else

615 uint64_t ByteA = Imm & 0xff00000000000000ULL;

616 uint64_t ByteB = Imm & 0x00ff000000000000ULL;

617 uint64_t ByteC = Imm & 0x0000ff0000000000ULL;

618 uint64_t ByteD = Imm & 0x000000ff00000000ULL;

619 uint64_t ByteE = Imm & 0x00000000ff000000ULL;

620 uint64_t ByteF = Imm & 0x0000000000ff0000ULL;

621 uint64_t ByteG = Imm & 0x000000000000ff00ULL;

622 uint64_t ByteH = Imm & 0x00000000000000ffULL;

623

624 return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&

625 (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&

626 (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&

627 (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&

628 (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&

629 (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&

630 (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&

631 (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);

632#endif

633}

634

636 uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;

637 uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;

638 uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;

639 uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;

640 uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;

641 uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;

642 uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;

643 uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;

644

646 EncVal <<= 1;

647 EncVal |= BitB;

648 EncVal <<= 1;

649 EncVal |= BitC;

650 EncVal <<= 1;

651 EncVal |= BitD;

652 EncVal <<= 1;

653 EncVal |= BitE;

654 EncVal <<= 1;

655 EncVal |= BitF;

656 EncVal <<= 1;

657 EncVal |= BitG;

658 EncVal <<= 1;

659 EncVal |= BitH;

660 return EncVal;

661}

662

665 if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;

666 if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;

667 if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;

668 if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;

669 if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;

670 if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;

671 if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;

672 if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;

673 return EncVal;

674}

675

676

678 uint64_t BString = (Imm & 0x7E000000ULL) >> 25;

679 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&

680 (BString == 0x1f || BString == 0x20) &&

681 ((Imm & 0x0007ffff0007ffffULL) == 0);

682}

683

685 uint8_t BitA = (Imm & 0x80000000ULL) != 0;

686 uint8_t BitB = (Imm & 0x20000000ULL) != 0;

687 uint8_t BitC = (Imm & 0x01000000ULL) != 0;

688 uint8_t BitD = (Imm & 0x00800000ULL) != 0;

689 uint8_t BitE = (Imm & 0x00400000ULL) != 0;

690 uint8_t BitF = (Imm & 0x00200000ULL) != 0;

691 uint8_t BitG = (Imm & 0x00100000ULL) != 0;

692 uint8_t BitH = (Imm & 0x00080000ULL) != 0;

693

695 EncVal <<= 1;

696 EncVal |= BitB;

697 EncVal <<= 1;

698 EncVal |= BitC;

699 EncVal <<= 1;

700 EncVal |= BitD;

701 EncVal <<= 1;

702 EncVal |= BitE;

703 EncVal <<= 1;

704 EncVal |= BitF;

705 EncVal <<= 1;

706 EncVal |= BitG;

707 EncVal <<= 1;

708 EncVal |= BitH;

709 return EncVal;

710}

711

714 if (Imm & 0x80) EncVal |= 0x80000000ULL;

715 if (Imm & 0x40) EncVal |= 0x3e000000ULL;

716 else EncVal |= 0x40000000ULL;

717 if (Imm & 0x20) EncVal |= 0x01000000ULL;

718 if (Imm & 0x10) EncVal |= 0x00800000ULL;

719 if (Imm & 0x08) EncVal |= 0x00400000ULL;

720 if (Imm & 0x04) EncVal |= 0x00200000ULL;

721 if (Imm & 0x02) EncVal |= 0x00100000ULL;

722 if (Imm & 0x01) EncVal |= 0x00080000ULL;

723 return (EncVal << 32) | EncVal;

724}

725

726

728 uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;

729 return ((BString == 0xff || BString == 0x100) &&

730 ((Imm & 0x0000ffffffffffffULL) == 0));

731}

732

734 uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;

735 uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;

736 uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;

737 uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;

738 uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;

739 uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;

740 uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;

741 uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;

742

744 EncVal <<= 1;

745 EncVal |= BitB;

746 EncVal <<= 1;

747 EncVal |= BitC;

748 EncVal <<= 1;

749 EncVal |= BitD;

750 EncVal <<= 1;

751 EncVal |= BitE;

752 EncVal <<= 1;

753 EncVal |= BitF;

754 EncVal <<= 1;

755 EncVal |= BitG;

756 EncVal <<= 1;

757 EncVal |= BitH;

758 return EncVal;

759}

760

763 if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;

764 if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;

765 else EncVal |= 0x4000000000000000ULL;

766 if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;

767 if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;

768 if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;

769 if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;

770 if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;

771 if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;

772 return (EncVal << 32) | EncVal;

773}

774

775

776template

778 auto Parts = bit_cast<std::array<T, sizeof(int64_t) / sizeof(T)>>(Imm);

780}

781

782

783template

785

786

787

788 int64_t Mask = ~int64_t(std::numeric_limits<std::make_unsigned_t>::max());

789 if ((Imm & Mask) != 0 && (Imm & Mask) != Mask)

790 return false;

791

792

793

794 if (Imm & 0xff)

795 return int8_t(Imm) == T(Imm);

796

797

798

799 if (Imm & 0xff00)

800 return int16_t(Imm) == T(Imm);

801

802 return Imm == 0;

803}

804

805

806template

808 bool IsInt8t = std::is_same<int8_t, std::make_signed_t>::value ||

809 std::is_same<int8_t, T>::value;

810 return uint8_t(Imm) == Imm || (!IsInt8t && uint16_t(Imm & ~0xff) == Imm);

811}

812

813

816 return false;

817

821

823 return false;

825 return false;

827 return false;

829}

830

832 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)

833 if ((Value & ~(0xffffULL << Shift)) == 0)

834 return true;

835

836 return false;

837}

838

840 if (RegWidth == 32)

841 Value &= 0xffffffffULL;

842

843

844 if (Value == 0 && Shift != 0)

845 return false;

846

847 return (Value & ~(0xffffULL << Shift)) == 0;

848}

849

851

853 return false;

854

856 if (RegWidth == 32)

857 Value &= 0xffffffffULL;

858

860}

861

864 return true;

865

866

868 if (RegWidth == 32)

869 Value &= 0xffffffffULL;

870

872}

873

874static inline bool isSVECpyDupImm(int SizeInBits, int64_t Val, int32_t &Imm,

875 int32_t &Shift) {

876 switch (SizeInBits) {

877 case 8:

878

879 Shift = 0;

880 Imm = Val & 0xFF;

881 return true;

882 case 16:

883 case 32:

884 case 64:

885

886 if (Val >= -128 && Val <= 127) {

887 Shift = 0;

888 Imm = Val & 0xFF;

889 return true;

890 }

891

892 if (Val >= -32768 && Val <= 32512 && Val % 256 == 0) {

893 Shift = 8;

894 Imm = (Val >> 8) & 0xFF;

895 return true;

896 }

897 break;

898 default:

899 break;

900 }

901 return false;

902}

903

904}

905

906}

907

908#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file declares a class to represent arbitrary precision floating point values and provide a varie...

This file implements a class to represent arbitrary precision integral constant values and operations...

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This file implements the C++20 header.

APInt bitcastToAPInt() const

Class for arbitrary precision integers.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

AArch64_AM - AArch64 Addressing Mode Stuff.

Definition AArch64AddressingModes.h:26

static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)

isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...

Definition AArch64AddressingModes.h:321

static bool isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)

Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.

Definition AArch64AddressingModes.h:814

static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth)

Definition AArch64AddressingModes.h:831

static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)

Definition AArch64AddressingModes.h:850

static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)

decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...

Definition AArch64AddressingModes.h:293

static unsigned getMemExtendImm(AArch64_AM::ShiftExtendType ET, bool DoShift)

getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be...

Definition AArch64AddressingModes.h:200

static unsigned getShiftValue(unsigned Imm)

getShiftValue - Extract the shift value.

Definition AArch64AddressingModes.h:85

static uint64_t decodeAdvSIMDModImmType4(uint8_t Imm)

Definition AArch64AddressingModes.h:505

static bool isLogicalImmediate(uint64_t imm, unsigned regSize)

isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the...

Definition AArch64AddressingModes.h:275

static uint8_t encodeAdvSIMDModImmType2(uint64_t Imm)

Definition AArch64AddressingModes.h:471

static bool isSVEAddSubImm(int64_t Imm)

Returns true if Imm is valid for ADD/SUB.

Definition AArch64AddressingModes.h:807

static bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)

processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of ...

Definition AArch64AddressingModes.h:213

static bool isAdvSIMDModImmType9(uint64_t Imm)

Definition AArch64AddressingModes.h:573

static uint64_t decodeAdvSIMDModImmType2(uint8_t Imm)

Definition AArch64AddressingModes.h:475

static bool isAdvSIMDModImmType4(uint64_t Imm)

Definition AArch64AddressingModes.h:496

static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)

getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...

Definition AArch64AddressingModes.h:170

static uint64_t decodeAdvSIMDModImmType12(uint8_t Imm)

Definition AArch64AddressingModes.h:761

static bool isAdvSIMDModImmType5(uint64_t Imm)

Definition AArch64AddressingModes.h:511

static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)

Definition AArch64AddressingModes.h:862

static unsigned getArithShiftValue(unsigned Imm)

getArithShiftValue - get the arithmetic shift value.

Definition AArch64AddressingModes.h:118

static uint64_t decodeAdvSIMDModImmType11(uint8_t Imm)

Definition AArch64AddressingModes.h:712

static int getFP32Imm(const APInt &Imm)

getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.

Definition AArch64AddressingModes.h:393

static float getFPImmFloat(unsigned Imm)

Definition AArch64AddressingModes.h:343

static AArch64_AM::ShiftExtendType getMemExtendType(unsigned Imm)

getExtendType - Extract the extend type for the offset operand of loads/stores.

Definition AArch64AddressingModes.h:184

static uint8_t encodeAdvSIMDModImmType7(uint64_t Imm)

Definition AArch64AddressingModes.h:548

static uint64_t decodeAdvSIMDModImmType1(uint8_t Imm)

Definition AArch64AddressingModes.h:460

static uint8_t encodeAdvSIMDModImmType12(uint64_t Imm)

Definition AArch64AddressingModes.h:733

static uint8_t encodeAdvSIMDModImmType10(uint64_t Imm)

Definition AArch64AddressingModes.h:635

static uint8_t encodeAdvSIMDModImmType9(uint64_t Imm)

Definition AArch64AddressingModes.h:579

static bool isSVEMaskOfIdenticalElements(int64_t Imm)

Returns true if Imm is the concatenation of a repeating pattern of type T.

Definition AArch64AddressingModes.h:777

static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)

Definition AArch64AddressingModes.h:839

ShiftExtendType

Definition AArch64AddressingModes.h:32

@ SXTW

Definition AArch64AddressingModes.h:47

@ LSL

Definition AArch64AddressingModes.h:34

@ UXTW

Definition AArch64AddressingModes.h:42

@ ASR

Definition AArch64AddressingModes.h:36

@ InvalidShiftExtend

Definition AArch64AddressingModes.h:33

@ UXTB

Definition AArch64AddressingModes.h:40

@ MSL

Definition AArch64AddressingModes.h:38

@ LSR

Definition AArch64AddressingModes.h:35

@ UXTH

Definition AArch64AddressingModes.h:41

@ ROR

Definition AArch64AddressingModes.h:37

@ SXTB

Definition AArch64AddressingModes.h:45

@ UXTX

Definition AArch64AddressingModes.h:43

@ SXTX

Definition AArch64AddressingModes.h:48

@ SXTH

Definition AArch64AddressingModes.h:46

static uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize)

encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of th...

Definition AArch64AddressingModes.h:282

static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)

getShiftName - Get the string encoding for the shift type.

Definition AArch64AddressingModes.h:52

static bool isAdvSIMDModImmType7(uint64_t Imm)

Definition AArch64AddressingModes.h:543

static uint64_t decodeAdvSIMDModImmType3(uint8_t Imm)

Definition AArch64AddressingModes.h:490

static uint64_t decodeAdvSIMDModImmType7(uint8_t Imm)

Definition AArch64AddressingModes.h:552

unsigned getExtendEncoding(AArch64_AM::ShiftExtendType ET)

Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 =...

Definition AArch64AddressingModes.h:151

static bool isSVECpyImm(int64_t Imm)

Returns true if Imm is valid for CPY/DUP.

Definition AArch64AddressingModes.h:784

static uint8_t encodeAdvSIMDModImmType5(uint64_t Imm)

Definition AArch64AddressingModes.h:517

static int getFP64Imm(const APInt &Imm)

getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.

Definition AArch64AddressingModes.h:421

static uint64_t ror(uint64_t elt, unsigned size)

Definition AArch64AddressingModes.h:205

static bool isAdvSIMDModImmType10(uint64_t Imm)

Definition AArch64AddressingModes.h:593

static AArch64_AM::ShiftExtendType getExtendType(unsigned Imm)

getExtendType - Extract the extend type for operands of arithmetic ops.

Definition AArch64AddressingModes.h:123

static int getFP16Imm(const APInt &Imm)

getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.

Definition AArch64AddressingModes.h:367

static uint64_t decodeAdvSIMDModImmType9(uint8_t Imm)

Definition AArch64AddressingModes.h:583

static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)

Definition AArch64AddressingModes.h:663

static uint64_t decodeAdvSIMDModImmType5(uint8_t Imm)

Definition AArch64AddressingModes.h:521

static uint64_t decodeAdvSIMDModImmType8(uint8_t Imm)

Definition AArch64AddressingModes.h:563

static uint8_t encodeAdvSIMDModImmType8(uint64_t Imm)

Definition AArch64AddressingModes.h:568

static bool isAdvSIMDModImmType12(uint64_t Imm)

Definition AArch64AddressingModes.h:727

static uint8_t encodeAdvSIMDModImmType11(uint64_t Imm)

Definition AArch64AddressingModes.h:684

static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)

Definition AArch64AddressingModes.h:138

static bool isSVECpyDupImm(int SizeInBits, int64_t Val, int32_t &Imm, int32_t &Shift)

Definition AArch64AddressingModes.h:874

static bool isAdvSIMDModImmType11(uint64_t Imm)

Definition AArch64AddressingModes.h:677

static uint8_t encodeAdvSIMDModImmType6(uint64_t Imm)

Definition AArch64AddressingModes.h:533

static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)

getShiftType - Extract the shift type.

Definition AArch64AddressingModes.h:73

static bool isAdvSIMDModImmType8(uint64_t Imm)

Definition AArch64AddressingModes.h:558

static uint8_t encodeAdvSIMDModImmType4(uint64_t Imm)

Definition AArch64AddressingModes.h:501

static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)

getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...

Definition AArch64AddressingModes.h:98

static bool isAdvSIMDModImmType6(uint64_t Imm)

Definition AArch64AddressingModes.h:527

static bool getMemDoShift(unsigned Imm)

getMemDoShift - Extract the "do shift" flag value for load/store instructions.

Definition AArch64AddressingModes.h:178

static uint8_t encodeAdvSIMDModImmType1(uint64_t Imm)

Definition AArch64AddressingModes.h:456

static uint8_t encodeAdvSIMDModImmType3(uint64_t Imm)

Definition AArch64AddressingModes.h:486

static bool isAdvSIMDModImmType2(uint64_t Imm)

Definition AArch64AddressingModes.h:466

static uint64_t decodeAdvSIMDModImmType6(uint8_t Imm)

Definition AArch64AddressingModes.h:537

static bool isAdvSIMDModImmType3(uint64_t Imm)

Definition AArch64AddressingModes.h:481

static bool isAdvSIMDModImmType1(uint64_t Imm)

Definition AArch64AddressingModes.h:451

This is an optimization pass for GlobalISel generic memory operations.

GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)

auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)

Get the size of a range.

int countr_one(T Value)

Count the number of ones from the least significant bit to the first zero bit.

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

constexpr bool isShiftedMask_64(uint64_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...

int countl_zero(T Val)

Count number of 0's from the most significant bit to the least stopping at the first 1.

int countl_one(T Value)

Count the number of ones from the most significant bit to the first zero bit.

To bit_cast(const From &from) noexcept

bool all_equal(std::initializer_list< T > Values)

Returns true if all Values in the initializer lists are equal or the list.