LLVM: llvm::AArch64_AM Namespace Reference (original) (raw)

AArch64_AM - AArch64 Addressing Mode Stuff. More...

Enumerations
enum ShiftExtendType { InvalidShiftExtend = -1 , LSL = 0 , LSR, ASR, ROR, MSL, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX }
Functions
static const char * getShiftExtendName (AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
static AArch64_AM::ShiftExtendType getShiftType (unsigned Imm)
getShiftType - Extract the shift type.
static unsigned getShiftValue (unsigned Imm)
getShiftValue - Extract the shift value.
static unsigned getShifterImm (AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm
static unsigned getArithShiftValue (unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
static AArch64_AM::ShiftExtendType getExtendType (unsigned Imm)
getExtendType - Extract the extend type for operands of arithmetic ops.
static AArch64_AM::ShiftExtendType getArithExtendType (unsigned Imm)
unsigned getExtendEncoding (AArch64_AM::ShiftExtendType ET)
Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx.
static unsigned getArithExtendImm (AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3
static bool getMemDoShift (unsigned Imm)
getMemDoShift - Extract the "do shift" flag value for load/store instructions.
static AArch64_AM::ShiftExtendType getMemExtendType (unsigned Imm)
getExtendType - Extract the extend type for the offset operand of loads/stores.
static unsigned getMemExtendImm (AArch64_AM::ShiftExtendType ET, bool DoShift)
getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift
static uint64_t ror (uint64_t elt, unsigned size)
static bool processLogicalImmediate (uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.
static bool isLogicalImmediate (uint64_t imm, unsigned regSize)
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size.
static uint64_t encodeLogicalImmediate (uint64_t imm, unsigned regSize)
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.
static uint64_t decodeLogicalImmediate (uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits.
static bool isValidDecodeLogicalImmediate (uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits.
static float getFPImmFloat (unsigned Imm)
static int getFP16Imm (const APInt &Imm)
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
static int getFP16Imm (const APFloat &FPImm)
static int getFP32Imm (const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
static int getFP32Imm (const APFloat &FPImm)
static int getFP64Imm (const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
static int getFP64Imm (const APFloat &FPImm)
static bool isAdvSIMDModImmType1 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType1 (uint8_t Imm)
static bool isAdvSIMDModImmType2 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType2 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType2 (uint8_t Imm)
static bool isAdvSIMDModImmType3 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType3 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType3 (uint8_t Imm)
static bool isAdvSIMDModImmType4 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType4 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType4 (uint8_t Imm)
static bool isAdvSIMDModImmType5 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType5 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType5 (uint8_t Imm)
static bool isAdvSIMDModImmType6 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType6 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType6 (uint8_t Imm)
static bool isAdvSIMDModImmType7 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType7 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType7 (uint8_t Imm)
static bool isAdvSIMDModImmType8 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType8 (uint8_t Imm)
static uint8_t encodeAdvSIMDModImmType8 (uint64_t Imm)
static bool isAdvSIMDModImmType9 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType9 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType9 (uint8_t Imm)
static bool isAdvSIMDModImmType10 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType10 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType10 (uint8_t Imm)
static bool isAdvSIMDModImmType11 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType11 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType11 (uint8_t Imm)
static bool isAdvSIMDModImmType12 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType12 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType12 (uint8_t Imm)
template<typename T>
static bool isSVEMaskOfIdenticalElements (int64_t Imm)
Returns true if Imm is the concatenation of a repeating pattern of type T.
template<typename T>
static bool isSVECpyImm (int64_t Imm)
Returns true if Imm is valid for CPY/DUP.
template<typename T>
static bool isSVEAddSubImm (int64_t Imm)
Returns true if Imm is valid for ADD/SUB.
static bool isSVEMoveMaskPreferredLogicalImmediate (int64_t Imm)
Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
static bool isAnyMOVZMovAlias (uint64_t Value, int RegWidth)
static bool isMOVZMovAlias (uint64_t Value, int Shift, int RegWidth)
static bool isMOVNMovAlias (uint64_t Value, int Shift, int RegWidth)
static bool isAnyMOVWMovAlias (uint64_t Value, int RegWidth)
static bool isSVECpyDupImm (int SizeInBits, int64_t Val, int32_t &Imm, int32_t &Shift)

AArch64_AM - AArch64 Addressing Mode Stuff.

◆ ShiftExtendType

Enumerator
InvalidShiftExtend
LSL
LSR
ASR
ROR
MSL
UXTB
UXTH
UXTW
UXTX
SXTB
SXTH
SXTW
SXTX

Definition at line 32 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType1()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType1 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType10()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType10 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType11()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType11 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType12()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType12 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType2()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType2 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType3()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType3 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType4()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType4 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType5()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType5 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType6()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType6 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType7()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType7 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType8()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType8 ( uint8_t Imm) inlinestatic

◆ decodeAdvSIMDModImmType9()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType9 ( uint8_t Imm) inlinestatic

◆ decodeLogicalImmediate()

◆ encodeAdvSIMDModImmType1()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType1 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType10()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType10 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType11()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType11 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType12()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType12 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType2()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType2 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType3()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType3 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType4()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType4 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType5()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType5 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType6()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType6 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType7()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType7 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType8()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType8 ( uint64_t Imm) inlinestatic

◆ encodeAdvSIMDModImmType9()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType9 ( uint64_t Imm) inlinestatic

◆ encodeLogicalImmediate()

◆ getArithExtendImm()

◆ getArithExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getArithExtendType ( unsigned Imm) inlinestatic

◆ getArithShiftValue()

◆ getExtendEncoding()

unsigned llvm::AArch64_AM::getExtendEncoding ( AArch64_AM::ShiftExtendType ET) inline

◆ getExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getExtendType ( unsigned Imm) inlinestatic

getExtendType - Extract the extend type for operands of arithmetic ops.

Definition at line 123 of file AArch64AddressingModes.h.

References assert(), llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.

Referenced by getArithExtendType(), getMemExtendType(), and llvm::AArch64InstrInfo::insertSelect().

◆ getFP16Imm() [1/2]

int llvm::AArch64_AM::getFP16Imm ( const APFloat & FPImm) inlinestatic

◆ getFP16Imm() [2/2]

int llvm::AArch64_AM::getFP16Imm ( const APInt & Imm) inlinestatic

◆ getFP32Imm() [1/2]

int llvm::AArch64_AM::getFP32Imm ( const APFloat & FPImm) inlinestatic

◆ getFP32Imm() [2/2]

int llvm::AArch64_AM::getFP32Imm ( const APInt & Imm) inlinestatic

◆ getFP64Imm() [1/2]

int llvm::AArch64_AM::getFP64Imm ( const APFloat & FPImm) inlinestatic

◆ getFP64Imm() [2/2]

int llvm::AArch64_AM::getFP64Imm ( const APInt & Imm) inlinestatic

◆ getFPImmFloat()

float llvm::AArch64_AM::getFPImmFloat ( unsigned Imm) inlinestatic

◆ getMemDoShift()

bool llvm::AArch64_AM::getMemDoShift ( unsigned Imm) inlinestatic

getMemDoShift - Extract the "do shift" flag value for load/store instructions.

Definition at line 178 of file AArch64AddressingModes.h.

◆ getMemExtendImm()

getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift

Definition at line 200 of file AArch64AddressingModes.h.

References getExtendEncoding().

◆ getMemExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getMemExtendType ( unsigned Imm) inlinestatic

◆ getShifterImm()

getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm

Definition at line 98 of file AArch64AddressingModes.h.

References ASR, assert(), llvm_unreachable, LSL, LSR, MSL, and ROR.

Referenced by llvm::AArch64InstrInfo::copyPhysReg(), emitFrameOffsetAdj(), llvm::AArch64_IMM::expandMOVImm(), expandMOVImmSimple(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::AArch64InstrInfo::probedStackAlloc(), tryOrrWithShift(), trySequenceOfOnes(), and tryToreplicateChunks().

◆ getShiftExtendName()

const char * llvm::AArch64_AM::getShiftExtendName ( AArch64_AM::ShiftExtendType ST) inlinestatic

getShiftName - Get the string encoding for the shift type.

Definition at line 52 of file AArch64AddressingModes.h.

References ASR, llvm_unreachable, LSL, LSR, MSL, ROR, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.

Referenced by llvm::AArch64InstPrinter::printArithExtend(), and llvm::AArch64InstPrinter::printShifter().

◆ getShiftType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getShiftType ( unsigned Imm) inlinestatic

◆ getShiftValue()

◆ isAdvSIMDModImmType1()

bool llvm::AArch64_AM::isAdvSIMDModImmType1 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType10()

bool llvm::AArch64_AM::isAdvSIMDModImmType10 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType11()

bool llvm::AArch64_AM::isAdvSIMDModImmType11 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType12()

bool llvm::AArch64_AM::isAdvSIMDModImmType12 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType2()

bool llvm::AArch64_AM::isAdvSIMDModImmType2 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType3()

bool llvm::AArch64_AM::isAdvSIMDModImmType3 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType4()

bool llvm::AArch64_AM::isAdvSIMDModImmType4 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType5()

bool llvm::AArch64_AM::isAdvSIMDModImmType5 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType6()

bool llvm::AArch64_AM::isAdvSIMDModImmType6 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType7()

bool llvm::AArch64_AM::isAdvSIMDModImmType7 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType8()

bool llvm::AArch64_AM::isAdvSIMDModImmType8 ( uint64_t Imm) inlinestatic

◆ isAdvSIMDModImmType9()

bool llvm::AArch64_AM::isAdvSIMDModImmType9 ( uint64_t Imm) inlinestatic

◆ isAnyMOVWMovAlias()

bool llvm::AArch64_AM::isAnyMOVWMovAlias ( uint64_t Value, int RegWidth ) inlinestatic

◆ isAnyMOVZMovAlias()

bool llvm::AArch64_AM::isAnyMOVZMovAlias ( uint64_t Value, int RegWidth ) inlinestatic

◆ isLogicalImmediate()

◆ isMOVNMovAlias()

bool llvm::AArch64_AM::isMOVNMovAlias ( uint64_t Value, int Shift, int RegWidth ) inlinestatic

◆ isMOVZMovAlias()

bool llvm::AArch64_AM::isMOVZMovAlias ( uint64_t Value, int Shift, int RegWidth ) inlinestatic

◆ isSVEAddSubImm()

template<typename T>

bool llvm::AArch64_AM::isSVEAddSubImm ( int64_t Imm) inlinestatic

◆ isSVECpyDupImm()

bool llvm::AArch64_AM::isSVECpyDupImm ( int SizeInBits, int64_t Val, int32_t & Imm, int32_t & Shift ) inlinestatic

◆ isSVECpyImm()

template<typename T>

bool llvm::AArch64_AM::isSVECpyImm ( int64_t Imm) inlinestatic

◆ isSVEMaskOfIdenticalElements()

template<typename T>

bool llvm::AArch64_AM::isSVEMaskOfIdenticalElements ( int64_t Imm) inlinestatic

◆ isSVEMoveMaskPreferredLogicalImmediate()

bool llvm::AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate ( int64_t Imm) inlinestatic

◆ isValidDecodeLogicalImmediate()

◆ processLogicalImmediate()

processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.

If so, return true with "encoding" set to the encoded value in the form N:immr:imms.

Definition at line 213 of file AArch64AddressingModes.h.

References assert(), llvm::countl_one(), llvm::countr_one(), llvm::countr_zero(), I, llvm::isShiftedMask_64(), N, RegSize, and Size.

Referenced by canUseOrr(), encodeLogicalImmediate(), llvm::AArch64_IMM::expandMOVImm(), isLogicalImmediate(), tryAndOfLogicalImmediates(), tryEorOfLogicalImmediates(), tryOrrOfLogicalImmediates(), and trySequenceOfOnes().

◆ ror()