AArch64ISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H

15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H

24namespace llvm {

56}

62class AArch64Subtarget;

65public:

74 SDValue N1) const override;

85 const APInt &DemandedElts,

87 unsigned Depth = 0) const override;

90 const APInt &DemandedElts,

92 unsigned Depth) const override;

100 return MVT::i32;

101 } else {

102

103

104

105

106 return MVT::i64;

107 }

108 }

109

114

116 const APInt &DemandedElts,

117 TargetLoweringOpt &TLO) const override;

118

120

121

122

124 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),

126 unsigned *Fast = nullptr) const override;

127

131 unsigned *Fast = nullptr) const override;

132

133

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142

144

146 bool ForCodeSize) const override;

147

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158 EVT VT) const override;

159

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181 unsigned Opcode, bool Op0IsDef) const;

183

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211 unsigned Intrinsic) const override;

212

214 std::optional ByteOffset) const override;

215

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237 const APInt &GapMask) const override;

240 const APInt &GapMask) const override;

241

244

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254 SDValue ConstNode) const override;

255

257

259 const AttributeList &FuncAttributes) const override;

260

262 const AttributeList &FuncAttributes) const override;

263

264

265

267 unsigned AS,

269

271 int64_t MaxOffset) const override;

272

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277 EVT VT) const override;

279

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307 EVT VT = Y.getValueType();

308

310 return false;

311

313 }

314

316 unsigned SelectOpcode, SDValue X,

318

319

320

322 Type *Ty) const override;

323

324

325

327 unsigned Index) const override;

328

330 bool MathUsed) const override {

331

332

334 }

335

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339 EVT VT) const override;

340

345

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352 bool

354

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389 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;

390

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406 return V.getValueType().isScalarInteger();

407 }

408

410 EVT VT = Y.getValueType();

411

414

416 return true;

417

419 }

420

423 unsigned OldShiftOpcode, unsigned NewShiftOpcode,

425

428 unsigned ExpansionFactor) const override;

429

431 unsigned KeptBits) const override {

432

434 return false;

435

436 auto VTIsOk = [](EVT VT) -> bool {

437 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||

438 VT == MVT::i64;

439 };

440

441

442

444 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);

445 }

446

448

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497 bool &UseScalable) const;

498

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502 bool UseScalable) const;

503

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526 if (F.hasFnAttribute(Attribute::NoRedZone))

527 return 0;

528 return 128;

529 }

530

533

535 bool AllowUnknown = false) const override;

536

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549 bool InsertVectorLengthCheck = false) const;

550

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560 EVT VT) const override;

563 EVT VT) const override;

566 EVT &IntermediateVT,

567 unsigned &NumIntermediates,

568 MVT &RegisterVT) const override;

569

570

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574

576

577private:

578

579

581

582 bool isExtFreeImpl(const Instruction *Ext) const override;

583

584 void addTypeForNEON(MVT VT);

585 void addTypeForFixedLengthSVE(MVT VT);

586 void addDRType(MVT VT);

587 void addQRType(MVT VT);

588

589 bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override;

590

593

595 bool isVarArg,

599

602

603 SDValue LowerCall(CallLoweringInfo & ,

605

611 SDValue ThisVal, bool RequiresSMChange) const;

612

619

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631 bool

632 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;

633

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640 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;

641

644

646 bool isVarArg,

649

654

656 unsigned Flag) const;

658 unsigned Flag) const;

660 unsigned Flag) const;

662 unsigned Flag) const;

664 unsigned Flag) const;

665 template

667 template

668 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;

669 template

671 template

724 unsigned NewOp) const;

767

769

778 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,

799

805 int &ExtraSteps, bool &UseOneConst,

806 bool Reciprocal) const override;

808 int &ExtraSteps) const override;

814

815 ConstraintType getConstraintType(StringRef Constraint) const override;

818

819

820

822 getSingleConstraintMatchWeight(AsmOperandInfo &info,

823 const char *constraint) const override;

824

825 std::pair<unsigned, const TargetRegisterClass *>

827 StringRef Constraint, MVT VT) const override;

828

829 const char *LowerXConstraint(EVT ConstraintVT) const override;

830

832 std::vector &Ops,

834

836 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {

837 if (ConstraintCode == "Q")

839

840

841

843 }

844

845

847 const SDLoc &DL,

848 const AsmOperandInfo &Constraint,

849 SelectionDAG &DAG) const override;

850

851 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;

852 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;

853 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;

854 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;

855 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;

856 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,

860 SelectionDAG &DAG) const override;

861 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,

863 SelectionDAG &DAG) const override;

865 bool IsPre, MachineRegisterInfo &MRI) const override;

866

867 void ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results,

868 SelectionDAG &DAG) const override;

869 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl &Results,

870 SelectionDAG &DAG) const;

871 void ReplaceExtractSubVectorResults(SDNode *N,

872 SmallVectorImpl &Results,

873 SelectionDAG &DAG) const;

874 void ReplaceGetActiveLaneMaskResults(SDNode *N,

875 SmallVectorImpl &Results,

876 SelectionDAG &DAG) const;

877

878 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;

879

880 void finalizeLowering(MachineFunction &MF) const override;

881

882 bool shouldLocalize(const MachineInstr &MI,

883 const TargetTransformInfo *TTI) const override;

884

885 bool SimplifyDemandedBitsForTargetNode(SDValue Op,

886 const APInt &OriginalDemandedBits,

887 const APInt &OriginalDemandedElts,

888 KnownBits &Known,

889 TargetLoweringOpt &TLO,

890 unsigned Depth) const override;

891

892 bool canCreateUndefOrPoisonForTargetNode(SDValue Op,

893 const APInt &DemandedElts,

894 const SelectionDAG &DAG,

896 unsigned Depth) const override;

897

898 bool isTargetCanonicalConstantNode(SDValue Op) const override;

899

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910 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;

911

912

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914 SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL,

915 EVT VT) const;

916

917 bool preferScalarizeSplat(SDNode *N) const override;

918

920

922

923 bool shouldScalarizeBinop(SDValue VecOp) const override {

924 return VecOp.getOpcode() == ISD::SETCC;

925 }

926

927 bool hasMultipleConditionRegisters(EVT VT) const override {

928 return VT.isScalableVector();

929 }

930};

931

933FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

934 const TargetLibraryInfo *libInfo);

935}

936

937}

938

939#endif

unsigned const MachineRegisterInfo * MRI

const TargetInstrInfo & TII

static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG)

static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)

static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)

static SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG)

static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Function Alias Analysis Results

static SDValue getTargetNode(ConstantPoolSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

iv Induction Variable Users

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

PowerPC Reduce CR logical Operation

static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))

static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)

static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)

static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)

static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG)

Lower SRA_PARTS and friends, which return two i32 values and take a 2 x i32 value to shift plus a shi...

static SDValue LowerAVG(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerMSTORE(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)

static SDValue LowerEXTEND_VECTOR_INREG(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...

If a physical register, this returns the register that receives the exception address on entry to an ...

bool isTruncateFree(Type *Ty1, Type *Ty2) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

bool supportSplitCSR(MachineFunction *MF) const override

Return true if the target supports that a subset of CSRs for the given machine function is handled ex...

Definition AArch64ISelLowering.h:462

SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, bool InsertVectorLengthCheck=false) const

If a change in streaming mode is required on entry to/return from a function call it emits and return...

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override

Return true if it is profitable to fold a pair of shifts into a mask.

Definition AArch64ISelLowering.h:306

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset) const override

Return true if it is profitable to reduce a load to a smaller type.

void initializeSplitCSR(MachineBasicBlock *Entry) const override

Perform necessary initialization to handle a subset of CSRs explicitly via copies.

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

bool hasAndNotCompare(SDValue V) const override

Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...

Definition AArch64ISelLowering.h:404

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Return the preferred vector type legalization action.

EVT getPromotedVTForPredicate(EVT VT) const

bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override

Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.

unsigned getVaListSizeInBits(const DataLayout &DL) const override

Returns the size of the platform's va_list object.

MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const

void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override

Insert explicit copies in entry and exit blocks.

int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const override

Return the prefered common base offset.

bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...

bool shouldExpandCttzElements(EVT VT) const override

Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...

MachineBasicBlock * EmitInitTPIDR2Object(MachineInstr &MI, MachineBasicBlock *BB) const

bool lowerInterleavedStore(Instruction *Store, Value *Mask, ShuffleVectorInst *SVI, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved store into a stN intrinsic.

MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const

unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const

Returns the number of interleaved accesses that will be generated when lowering accesses of the given...

bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override

Return true if it is profitable to fold a pair of shifts into a mask.

bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

bool preferSelectsOverBooleanArithmetic(EVT VT) const override

Should we prefer selects to doing arithmetic on boolean types.

unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Certain targets require unusual breakdowns of certain types.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

Provide custom lowering hooks for some operations.

bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...

bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override

Returns if it's reasonable to merge stores to MemVT size.

bool shouldOptimizeMulOverflowWithZeroHighBits(LLVMContext &Context, EVT VT) const override

bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override

Definition AArch64ISelLowering.h:486

bool isIntDivCheap(EVT VT, AttributeList Attr) const override

Return true if integer divide is usually cheaper than a sequence of several shifts,...

bool shouldRemoveRedundantExtend(SDValue Op) const override

Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...

CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const

Selects the correct CCAssignFn for a given CallingConvention value.

bool supportPtrAuthBundles() const override

Return true if the target supports ptrauth operand bundles.

Definition AArch64ISelLowering.h:475

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

Return the ISD::SETCC ValueType.

bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override

Try to optimize extending or truncating conversion instructions (like zext, trunc,...

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override

This method returns a target specific FastISel object, or null if the target does not support "fast" ...

CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const

Selects the correct CCAssignFn for a given CallingConvention value.

bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask, IntrinsicInst *DI) const override

Lower a deinterleave intrinsic to a target specific load intrinsic.

MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

unsigned getVectorIdxWidth(const DataLayout &DL) const override

Returns the type to be used for the index operand vector operations.

Definition AArch64ISelLowering.h:110

bool hasInlineStackProbe(const MachineFunction &MF) const override

True if stack clash protection is enabled for this functions.

bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT, unsigned SelectOpcode, SDValue X, SDValue Y) const override

Return true if pulling a binary operation into a select with an identity constant is profitable.

bool isLegalICmpImmediate(int64_t) const override

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...

Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override

Perform a store-conditional operation to Addr.

bool preferIncOfAddToSubOfNot(EVT VT) const override

These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override

bool isOpSuitableForLSE128(const Instruction *I) const

bool isVScaleKnownToBeAPowerOfTwo() const override

Return true only if vscale must be a power of two.

Definition AArch64ISelLowering.h:551

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

void fixupPtrauthDiscriminator(MachineInstr &MI, MachineBasicBlock *BB, MachineOperand &IntDiscOp, MachineOperand &AddrDiscOp, const TargetRegisterClass *AddrDiscRC) const

Replace (0, vreg) discriminator components with the operands of blend or with (immediate,...

bool lowerInterleavedLoad(Instruction *Load, Value *Mask, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved load into a ldN intrinsic.

bool fallBackToDAGISel(const Instruction &Inst) const override

bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override

Return true if the target has native support for the specified value type and it is 'desirable' to us...

bool isLegalAddScalableImmediate(int64_t) const override

Return true if adding the specified scalable immediate is legal, that is the target has add instructi...

bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override

Try to convert math with an overflow comparison into the corresponding DAG node operation.

Definition AArch64ISelLowering.h:329

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override

Create the IR node for the given complex deinterleaving operation.

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override

Returns true if the target allows unaligned memory accesses of the specified type.

MachineBasicBlock * EmitCheckMatchingVL(MachineInstr &MI, MachineBasicBlock *MBB) const

unsigned getMaxSupportedInterleaveFactor() const override

Get the maximum supported factor for interleaved memory accesses.

Definition AArch64ISelLowering.h:232

bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const

Returns true if VecTy is a legal interleaved access type.

void insertSSPDeclarations(Module &M) const override

Inserts necessary declarations for SSP (stack protection) purpose.

bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override

For some targets, an LLVM struct type must be broken down into multiple simple types,...

Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const

bool isComplexDeinterleavingSupported() const override

Does this target support complex deinterleaving.

bool isZExtFree(Type *Ty1, Type *Ty2) const override

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...

EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override

SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const

MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override

If the target has a standard location for the unsafe stack pointer, returns the address of that locat...

bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override

Return if the target supports combining a chain like:

bool isProfitableToHoist(Instruction *I) const override

Check if it is profitable to hoist instruction in then/else to if.

bool isOpSuitableForRCPC3(const Instruction *I) const

MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

Definition AArch64ISelLowering.h:94

bool isCheapToSpeculateCttz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

Definition AArch64ISelLowering.h:394

unsigned getRedZoneSize(const Function &F) const

Definition AArch64ISelLowering.h:525

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

MachineBasicBlock * EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const

bool hasAndNot(SDValue Y) const override

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...

Definition AArch64ISelLowering.h:409

MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const

bool isCheapToSpeculateCtlz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition AArch64ISelLowering.h:398

bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override

Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ ...

MachineBasicBlock * EmitEntryPStateSM(MachineInstr &MI, MachineBasicBlock *BB) const

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override

Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...

bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override

In AArch64, true if FEAT_CPA is present.

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const

LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override

LLT returning variant.

bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override

GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...

Definition AArch64ISelLowering.h:295

bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override

Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <>...

MachineBasicBlock * EmitAllocateSMESaveBuffer(MachineInstr &MI, MachineBasicBlock *BB) const

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

bool needsFixedCatchObjects() const override

Used for exception handling on Win64.

MachineBasicBlock * EmitAllocateZABuffer(MachineInstr &MI, MachineBasicBlock *BB) const

const AArch64TargetMachine & getTM() const

unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override

Certain targets such as MIPS require that some types such as vectors are always broken down into scal...

Value * getIRStackGuard(IRBuilderBase &IRB) const override

If the target has a standard location for the stack protector cookie, returns the address of that loc...

bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

Returns the target specific optimal type for load and store operations as a result of memset,...

bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const override

bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override

Does this target support complex deinterleaving with the given operation and type.

bool isOpSuitableForLDPSTP(const Instruction *I) const

AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)

MachineBasicBlock * EmitGetSMESaveSize(MachineInstr &MI, MachineBasicBlock *BB) const

bool hasPairedLoad(EVT LoadedType, Align &RequiredAlignment) const override

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...

bool isLegalAddImmediate(int64_t) const override

Return true if the specified immediate is legal add immediate, that is the target has add instruction...

bool shouldConsiderGEPOffsetSplit() const override

bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...

Definition AArch64ISelLowering.h:430

bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override

Similar to isShuffleMaskLegal.

const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override

Returns a 0 terminated array of registers that can be safely used as scratch registers.

void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override

If a physical register, this returns the register that receives the exception typeid on entry to a la...

bool useLoadStackGuardNode(const Module &M) const override

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.

ArrayRef< MCPhysReg > getRoundingControlRegisters() const override

Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.

bool lowerInterleaveIntrinsicToStore(Instruction *Store, Value *Mask, ArrayRef< Value * > InterleaveValues) const override

Lower an interleave intrinsic to a target specific store intrinsic.

MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override

bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override

This method can be implemented by targets that want to expose additional information about sign bits ...

bool isDesirableToCommuteXorWithShift(const SDNode *N) const override

Returns false if N is a bit extraction pattern of (X >> C) & Mask.

bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override

Returns false if N is a bit extraction pattern of (X >> C) & Mask.

bool supportSwiftError() const override

Return true if the target supports swifterror attribute.

Definition AArch64ISelLowering.h:471

bool enableAggressiveFMAFusion(EVT VT) const override

Enable aggressive FMA fusion on targets that want it.

MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.

MachineBasicBlock * EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const

bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override

Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...

bool supportKCFIBundles() const override

Return true if the target supports kcfi operand bundles.

Definition AArch64ISelLowering.h:477

bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override

Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...

bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const

bool mergeStoresAfterLegalization(EVT VT) const override

SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

CCState - This class holds information needed while lowering arguments and return values.

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

Common base class shared among various IRBuilders.

A wrapper class for inspecting calls to intrinsic functions.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Represents a single loop in the control flow graph.

static MVT getIntegerVT(unsigned BitWidth)

Instructions::iterator instr_iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

MachineOperand class - Representation of each machine instruction operand.

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This instruction constructs a fixed permutation of two input vectors.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

Provides information about what library functions are available for the current target.

virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const

Try to convert math with an overflow comparison into the corresponding DAG node operation.

ShiftLegalizationStrategy

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

virtual bool softPromoteHalfType() const

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const

TargetLowering(const TargetLowering &)=delete

virtual unsigned combineRepeatedFPDivisors() const

Indicate whether this target prefers to combine FDIVs with the same divisor.

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Base class of all SIMD vector types.

A range adaptor for a pair of iterators.

ArrayRef< MCPhysReg > getFPRArgRegs()

Rounding

Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.

Definition AArch64ISelLowering.h:31

@ RZ

Definition AArch64ISelLowering.h:35

@ RN

Definition AArch64ISelLowering.h:32

@ rmMask

Definition AArch64ISelLowering.h:36

@ RP

Definition AArch64ISelLowering.h:33

@ RM

Definition AArch64ISelLowering.h:34

const unsigned StackProbeMaxLoopUnroll

Maximum number of iterations to unroll for a constant size probing loop.

Definition AArch64ISelLowering.h:54

const unsigned StackProbeMaxUnprobedStack

Maximum allowed number of unprobed bytes above SP at an ABI boundary.

Definition AArch64ISelLowering.h:51

const unsigned RoundingBitsPos

Definition AArch64ISelLowering.h:40

const uint64_t ReservedFPControlBits

Definition AArch64ISelLowering.h:43

ArrayRef< MCPhysReg > getGPRArgRegs()

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)

@ PTR64

Definition AArch64ISelLowering.h:59

@ PTR32_SPTR

Definition AArch64ISelLowering.h:59

@ PTR32_UPTR

Definition AArch64ISelLowering.h:59

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ CXX_FAST_TLS

Used for access functions.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

LoadExtType

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

This is an optimization pass for GlobalISel generic memory operations.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

ComplexDeinterleavingOperation

CodeGenOptLevel

Code generation optimization level.

AtomicOrdering

Atomic ordering for LLVM's memory model.

ComplexDeinterleavingRotation

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

@ Enabled

Convert any .debug_str_offsets tables to DWARF64 if needed.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Represent subnormal handling kind for floating point instruction inputs and outputs.

uint64_t getScalarSizeInBits() const

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

bool isVector() const

Return true if this is a vector value type.

bool isScalableVector() const

Return true if this is a vector type where the runtime length is machine dependent.

These are IR-level optimization flags that may be propagated to SDNodes.