AArch64Subtarget.cpp Source File (original) (raw)

30using namespace llvm;

32#define DEBUG_TYPE "aarch64-subtarget"

34#define GET_SUBTARGETINFO_CTOR

35#define GET_SUBTARGETINFO_TARGET_DESC

36#include "AArch64GenSubtargetInfo.inc"

48 "aarch64-macho-enable-nonlazybind",

49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),

53 cl::desc("Enable the use of AA during codegen."));

56 "aarch64-insert-extract-base-cost",

64 "registers, so they can't be used by register allocator. "

65 "Should only be used for testing register allocator."),

71 cl::desc("Override the variant of check applied "

72 "to authenticated LR during tail call"),

77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));

80 "aarch64-streaming-hazard-size",

81 cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."),

85 "aarch64-stack-hazard-size",

86 cl::desc("alias for -aarch64-streaming-hazard-size"),

94 cl::desc("Enable subreg liveness tracking"));

98 cl::desc("Prefer add+cnt over addvl/inc/dec"));

104}

105

106AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(

108 bool HasMinSize) {

109

110

111 if (CPUString.empty())

112 CPUString = "generic";

113

114 if (TuneCPUString.empty())

115 TuneCPUString = CPUString;

116

118 initializeProperties(HasMinSize);

119

120 return *this;

121}

122

123void AArch64Subtarget::initializeProperties(bool HasMinSize) {

124

125

126

129 break;

130 case Carmel:

132 break;

133 case CortexA35:

134 case CortexA53:

135 case CortexA55:

136 case CortexR82:

137 case CortexR82AE:

141 break;

142 case CortexA57:

147 break;

148 case CortexA65:

150 break;

151 case CortexA72:

152 case CortexA73:

153 case CortexA75:

157 break;

158 case CortexA76:

159 case CortexA77:

160 case CortexA78:

161 case CortexA78AE:

162 case CortexA78C:

163 case CortexX1:

167 break;

168 case CortexA510:

169 case CortexA520:

174 break;

175 case CortexA710:

176 case CortexA715:

177 case CortexA720:

178 case CortexA725:

179 case CortexX2:

180 case CortexX3:

181 case CortexX4:

182 case CortexX925:

187 break;

188 case A64FX:

197 break;

198 case MONAKA:

200 break;

201 case AppleA7:

202 case AppleA10:

203 case AppleA11:

204 case AppleA12:

205 case AppleA13:

206 case AppleA14:

207 case AppleA15:

208 case AppleA16:

209 case AppleA17:

210 case AppleM4:

216 case AppleA14:

217 case AppleA15:

218 case AppleA16:

219 case AppleA17:

220 case AppleM4:

222 break;

223 default:

224 break;

225 }

226 break;

227 case ExynosM3:

232 break;

233 case Falkor:

235

241 break;

242 case Kryo:

249

251 break;

252 case NeoverseE1:

254 break;

255 case NeoverseN1:

259 break;

260 case NeoverseV2:

261 case NeoverseV3:

266 case NeoverseN2:

267 case NeoverseN3:

272 break;

273 case NeoverseV1:

279 break;

280 case Neoverse512TVB:

284 break;

285 case Saphira:

287

289 break;

290 case ThunderX2T99:

298

300 break;

301 case ThunderX:

302 case ThunderXT88:

303 case ThunderXT81:

304 case ThunderXT83:

308

310 break;

311 case TSV110:

315 break;

316 case ThunderX3T110:

324

326 break;

327 case Ampere1:

328 case Ampere1A:

329 case Ampere1B:

334 break;

335 case Oryon:

341 break;

342 }

343

346}

347

351 unsigned MinSVEVectorSizeInBitsOverride,

352 unsigned MaxSVEVectorSizeInBitsOverride,

353 bool IsStreaming, bool IsStreamingCompatible,

354 bool HasMinSize)

356 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),

357 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),

358 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),

359 IsLittle(LittleEndian), IsStreaming(IsStreaming),

360 IsStreamingCompatible(IsStreamingCompatible),

362 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),

363 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),

364 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),

365 TLInfo(TM, *this) {

368

372

374

375

376

377

380

382

386 for (unsigned i = 0; i < 29; ++i) {

387 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))

389 }

390

391 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))

393

394 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))

396

398}

399

402}

403

406}

407

410}

411

414}

415

418}

419

420

421

422unsigned

425

426

429

430

431

432

433

436

437 if (!TM.shouldAssumeDSOLocal(GV)) {

440 }

444 }

445

446

447

448

452

453

454

455

456

457 if (AllowTaggedGlobals && !isa(GV->getValueType()))

459

461}

462

465

466

470

471

472 auto *F = dyn_cast(GV);

474 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))

476

480

481

484 }

486

487

489 }

490 }

491

492

494 }

495

497}

498

500 unsigned NumRegionInstrs) const {

501

502

505

506

507

509}

510

515 !Def->isInstr() || Use ->isInstr() ||

516 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&

517 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))

518 return;

519

520

521

526 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {

528 DefOpIdx = Op.getOperandNo();

529 }

530 }

531 }

532

533

538 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {

540 UseOpIdx = Op.getOperandNo();

541 break;

542 }

543 }

544 }

545

548}

549

552}

553

556 return false;

557

559 return true;

562 }

563

564 return false;

565}

566

567std::unique_ptr

569 return balanceFPOps() ? std::make_unique() : nullptr;

570}

571

573

574

575

576

580}

581

583

585

586

589 return hasSVE2() || hasSME();

590}

591

592

593

594

595

596

597

598

599

600

601

602

603

604

607

608

614

615

616

618}

619

620std::optional<uint16_t>

622 const Function &ParentFn) const {

623 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))

624 return std::nullopt;

625

626

628 (Twine(ParentFn.getName()) + " blockaddress").str());

629}

630

632 return getSchedModel().hasInstrSchedModel();

633}

This file describes how to lower LLVM calls to machine code calls.

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

This file declares the targeting of the Machinelegalizer class for AArch64.

#define AUTH_CHECK_METHOD_CL_VALUES_LR

This file declares the targeting of the RegisterBankInfo class for AArch64.

static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)

static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)

static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))

static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))

static cl::opt< bool > EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking", cl::init(false), cl::Hidden, cl::desc("Enable subreg liveness tracking"))

static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)

static cl::opt< unsigned > AArch64StreamingHazardSize("aarch64-streaming-hazard-size", cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."), cl::init(0), cl::Hidden)

static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))

static cl::alias AArch64StreamingStackHazardSize("aarch64-stack-hazard-size", cl::desc("alias for -aarch64-streaming-hazard-size"), cl::aliasopt(AArch64StreamingHazardSize))

static cl::opt< bool > UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden, cl::desc("Prefer add+cnt over addvl/inc/dec"))

static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)

static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)

#define LLVM_FALLTHROUGH

LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.

unsigned const TargetRegisterInfo * TRI

This class provides the information for the target register banks.

AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)

This constructor initializes the data members to match that of the specified triple.

BitVector ReserveXRegisterForRA

BitVector ReserveXRegister

const CallLowering * getCallLowering() const override

const AArch64RegisterInfo * getRegisterInfo() const override

TailFoldingOpts DefaultSVETFOpts

std::unique_ptr< InstructionSelector > InstSelector

ARMProcFamilyEnum ARMProcFamily

ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.

std::unique_ptr< RegisterBankInfo > RegBankInfo

bool useSmallAddressing() const

unsigned EpilogueVectorizationMinVF

void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override

bool enableEarlyIfConversion() const override

const InlineAsmLowering * getInlineAsmLowering() const override

unsigned MaxPrefetchIterationsAhead

unsigned getVectorInsertExtractBaseCost() const

bool enableMachinePipeliner() const override

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

std::optional< uint16_t > getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const

Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabl...

unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const

bool useAA() const override

uint8_t VectorInsertExtractBaseCost

const AArch64TargetLowering * getTargetLowering() const override

bool isTargetMachO() const

uint16_t PrefetchDistance

bool supportsAddressTopByteIgnored() const

CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.

Align PrefFunctionAlignment

const Triple & getTargetTriple() const

unsigned MinVectorRegisterBitWidth

void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override

void mirFileLoaded(MachineFunction &MF) const override

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

InstructionSelector * getInstructionSelector() const override

uint16_t MinPrefetchStride

unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

unsigned MaxJumpTableSize

bool isWindowsArm64EC() const

bool useScalarIncVL() const

Returns true to use the addvl/inc/dec instructions, as opposed to separate add + cnt instructions.

unsigned MinimumJumpTableEntries

const LegalizerInfo * getLegalizerInfo() const override

bool EnableSubregLiveness

std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override

uint8_t MaxInterleaveFactor

AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod(const MachineFunction &MF) const

Choose a method of checking LR before performing a tail call.

const RegisterBankInfo * getRegBankInfo() const override

unsigned MaxBytesForLoopAlignment

std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo

This class represents an Operation in the Expression.

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

bool hasExternalLinkage() const

bool hasExternalWeakLinkage() const

bool hasDLLImportStorageClass() const

bool hasInternalLinkage() const

Type * getValueType() const

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)

Computes the maximum size of a callframe.

bool isMaxCallFrameSizeComputed() const

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

getReg - Returns the register number.

Holds all the information related to register banks.

Wrapper class representing virtual and physical registers.

Kind getKind() const

Returns an enum value representing the kind of the dependence.

@ Data

Regular data dependence (aka true-dependence).

void setLatency(unsigned Lat)

Sets the latency for this edge.

unsigned getReg() const

Returns the register associated with this edge.

Scheduling unit. This is a node in the scheduling DAG.

size_type count(StringRef Key) const

count - Return 1 if the element is in the map, 0 otherwise.

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

StringSet - A wrapper for StringMap that provides set-like functionality.

std::pair< typename Base::iterator, bool > insert(StringRef key)

Primary interface to the complete machine description for the target machine.

Provide an instruction scheduling machine model to CodeGen passes.

unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const

Compute operand latency based on the available machine model.

Triple - Helper class for working with autoconf configuration names.

bool isDriverKit() const

Is this an Apple DriverKit triple.

bool isiOS() const

Is this an iOS triple.

VersionTuple getiOSVersion() const

Parse the version number as with getOSVersion.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

bool isFunctionTy() const

True if this is an instance of FunctionType.

A Use represents the edge between a Value definition and its users.

StringRef getName() const

Return a constant reference to the value's name.

Represents a version number in the form major[.minor[.subminor[.build]]].

int getNumOccurrences() const

@ MO_DLLIMPORT

MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...

@ MO_NC

MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.

@ MO_GOT

MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...

@ MO_ARM64EC_CALLMANGLE

MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...

@ MO_TAGGED

MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.

@ MO_COFFSTUB

MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....

AuthCheckMethod

Variants of check performed on an authenticated pointer.

@ HighBitsNoTBI

Check by comparing bits 62 and 61 of the authenticated address.

@ None

Do not check the value at all.

bool isX18ReservedByDefault(const Triple &TT)

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, const AArch64Subtarget &, const AArch64RegisterBankInfo &)

iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)

uint16_t getPointerAuthStableSipHash(StringRef S)

Compute a stable non-zero 16-bit hash of the given string.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

bool DisableLatencyHeuristic