LLVM: llvm::AArch64Subtarget Class Reference (original) (raw)

#include "[Target/AArch64/AArch64Subtarget.h](AArch64Subtarget%5F8h%5Fsource.html)"

Public Types
enum	ARMProcFamilyEnum : uint8_t { Generic }

Public Member Functions
	AArch64Subtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)
	This constructor initializes the data members to match that of the specified triple.
const AArch64SelectionDAGInfo *	getSelectionDAGInfo () const override
const AArch64FrameLowering *	getFrameLowering () const override
const AArch64TargetLowering *	getTargetLowering () const override
const AArch64InstrInfo *	getInstrInfo () const override
const AArch64RegisterInfo *	getRegisterInfo () const override
const CallLowering *	getCallLowering () const override
const InlineAsmLowering *	getInlineAsmLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RegisterBankInfo *	getRegBankInfo () const override
const Triple &	getTargetTriple () const
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
bool	enableSubRegLiveness () const override
bool	enableMachinePipeliner () const override
bool	useDFAforSMS () const override
ARMProcFamilyEnum	getProcFamily () const
	Returns ARM processor family.
bool	isAppleMLike () const
	Returns true if the processor is an Apple M-series or aligned A-series (A14 or newer).
bool	isXRaySupported () const override
bool	isStreaming () const
	Returns true if the function has a streaming body.
bool	isStreamingCompatible () const
	Returns true if the function has a streaming-compatible body.
unsigned	getStreamingHazardSize () const
	Returns the size of memory region that if accessed by both the CPU and the SME unit could result in a hazard.
bool	isNeonAvailable () const
	Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e.g.
bool	isSVEAvailable () const
	Returns true if the target has SVE and can use the full range of SVE instructions, for example because it knows the function is known not to be in streaming-SVE mode or when the target has FEAT_FA64 enabled.
bool	isStreamingSVEAvailable () const
	Returns true if the target has access to the streaming-compatible subset of SVE instructions.
bool	isSVEorStreamingSVEAvailable () const
	Returns true if the target has access to either the full range of SVE instructions, or the streaming-compatible subset of SVE instructions.
bool	isNonStreamingSVEorSME2Available () const
	Returns true if the target has access to either the full range of SVE instructions, or the streaming-compatible subset of SVE instructions available to SME2.
unsigned	getMinVectorRegisterBitWidth () const
bool	isXRegisterReserved (size_t i) const
bool	isXRegisterReservedForRA (size_t i) const
unsigned	getNumXRegisterReserved () const
bool	isLRReservedForRA () const
bool	isXRegCustomCalleeSaved (size_t i) const
bool	hasCustomCallingConv () const
bool	hasFusion () const
	Return true if the CPU supports any kind of instruction fusion.
unsigned	getEpilogueVectorizationMinVF () const
unsigned	getMaxInterleaveFactor () const
unsigned	getVectorInsertExtractBaseCost () const
unsigned	getCacheLineSize () const override
unsigned	getScatterOverhead () const
unsigned	getGatherOverhead () const
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
unsigned	getMaxBytesForLoopAlignment () const
unsigned	getMaximumJumpTableSize () const
unsigned	getMinimumJumpTableEntries () const
bool	supportsAddressTopByteIgnored () const
	CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
bool	isLittleEndian () const
bool	isTargetDarwin () const
bool	isTargetIOS () const
bool	isTargetLinux () const
bool	isTargetWindows () const
bool	isTargetAndroid () const
bool	isTargetFuchsia () const
bool	isWindowsArm64EC () const
bool	isTargetCOFF () const
bool	isTargetELF () const
bool	isTargetMachO () const
bool	isTargetILP32 () const
bool	useAA () const override
bool	addrSinkUsingGEPs () const override
bool	useSmallAddressing () const
bool	isX16X17Safer () const
	Returns whether the operating system makes it safer to store sensitive values in x16 and x17 as opposed to other registers.
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
	ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned	ClassifyGlobalReference (const GlobalValue *GV, const TargetMachine &TM) const
	ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget.
unsigned	classifyGlobalFunctionReference (const GlobalValue *GV, const TargetMachine &TM) const
unsigned char	classifyGlobalFunctionReference (const GlobalValue *GV) const override
	This function is design to compatible with the function def in other targets and escape build error about the virtual function def in base class TargetSubtargetInfo.
void	overrideSchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override
void	adjustSchedDependency (SUnit Def, int DefOpIdx, SUnit Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
bool	enableEarlyIfConversion () const override
std::unique_ptr< PBQPRAConstraint >	getCustomPBQPConstraints () const override
bool	isCallingConvWin64 (CallingConv::ID CC, bool IsVarArg) const
bool	swiftAsyncContextIsDynamicallySet () const
	Return whether FrameLowering should always set the "extended frame present" bit in FP, or set it based on a symbol in the runtime.
void	mirFileLoaded (MachineFunction &MF) const override
unsigned	getMaxSVEVectorSizeInBits () const
unsigned	getMinSVEVectorSizeInBits () const
unsigned	getSVEVectorSizeInBits () const
bool	useSVEForFixedLengthVectors () const
bool	useSVEForFixedLengthVectors (EVT VT) const
unsigned	getVScaleForTuning () const
TailFoldingOpts	getSVETailFoldingDefaultOpts () const
bool	useScalarIncVL () const
	Returns true to use the addvl/inc/dec instructions, as opposed to separate add + cnt instructions.
const char *	getChkStkName () const
AArch64PAuth::AuthCheckMethod	getAuthenticatedLRCheckMethod (const MachineFunction &MF) const
	Choose a method of checking LR before performing a tail call.
std::optional< uint16_t >	getPtrAuthBlockAddressDiscriminatorIfEnabled (const Function &ParentFn) const
	Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabled, or std::nullopt otherwise.

Protected Attributes
ARMProcFamilyEnum	ARMProcFamily = Generic
	ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned	MinVectorRegisterBitWidth = 64
unsigned	EpilogueVectorizationMinVF = 16
uint8_t	MaxInterleaveFactor = 2
uint8_t	VectorInsertExtractBaseCost = 2
uint16_t	CacheLineSize = 0
unsigned	ScatterOverhead = 10
unsigned	GatherOverhead = 10
uint16_t	PrefetchDistance = 0
uint16_t	MinPrefetchStride = 1
unsigned	MaxPrefetchIterationsAhead = UINT_MAX
Align	PrefFunctionAlignment
Align	PrefLoopAlignment
unsigned	MaxBytesForLoopAlignment = 0
unsigned	MinimumJumpTableEntries = 4
unsigned	MaxJumpTableSize = 0
BitVector	ReserveXRegister
BitVector	ReserveXRegisterForRA
BitVector	CustomCallSavedXRegs
bool	IsLittle
bool	IsStreaming
bool	IsStreamingCompatible
std::optional< unsigned >	StreamingHazardSize
unsigned	MinSVEVectorSizeInBits
unsigned	MaxSVEVectorSizeInBits
unsigned	VScaleForTuning = 1
TailFoldingOpts	DefaultSVETFOpts = TailFoldingOpts::Disabled
bool	EnableSubregLiveness
Triple	TargetTriple
	TargetTriple - What processor and OS we're targeting.
AArch64FrameLowering	FrameLowering
AArch64InstrInfo	InstrInfo
AArch64SelectionDAGInfo	TSInfo
AArch64TargetLowering	TLInfo
std::unique_ptr< CallLowering >	CallLoweringInfo
	GlobalISel related APIs.
std::unique_ptr< InlineAsmLowering >	InlineAsmLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RegisterBankInfo >	RegBankInfo

Definition at line 38 of file AArch64Subtarget.h.

◆ ARMProcFamilyEnum

AArch64Subtarget::AArch64Subtarget	(	const Triple &	TT,
StringRef	CPU,
StringRef	TuneCPU,
StringRef	FS,
const TargetMachine &	TM,
bool	LittleEndian,
unsigned	MinSVEVectorSizeInBitsOverride = 0,
unsigned	MaxSVEVectorSizeInBitsOverride = 0,
bool	IsStreaming = false,
bool	IsStreamingCompatible = false,
bool	HasMinSize = false )

This constructor initializes the data members to match that of the specified triple.

Definition at line 361 of file AArch64Subtarget.cpp.

References AArch64StreamingHazardSize, CallLoweringInfo, llvm::StringMap< ValueTy, AllocatorTy >::count(), llvm::createAArch64InstructionSelector(), CustomCallSavedXRegs, EnableSubregLiveness, EnableSubregLivenessTracking, llvm::from_range, getRegisterInfo(), getTargetLowering(), InlineAsmLoweringInfo, InstrInfo, InstSelector, IsLittle, IsStreaming, IsStreamingCompatible, llvm::AArch64::isX18ReservedByDefault(), Legalizer, MaxSVEVectorSizeInBits, MinSVEVectorSizeInBits, RegBankInfo, ReservedRegsForRA, ReserveXRegister, ReserveXRegisterForRA, StreamingHazardSize, TargetTriple, TLInfo, and TRI.

◆ addrSinkUsingGEPs()

bool llvm::AArch64Subtarget::addrSinkUsingGEPs ( ) const	inlineoverride

◆ adjustSchedDependency()

◆ classifyGlobalFunctionReference() [1/2]

This function is design to compatible with the function def in other targets and escape build error about the virtual function def in base class TargetSubtargetInfo.

Updeate me if AArch64 target need to use it.

Definition at line 361 of file AArch64Subtarget.h.

◆ classifyGlobalFunctionReference() [2/2]

Definition at line 478 of file AArch64Subtarget.cpp.

References ClassifyGlobalReference(), llvm::dyn_cast(), F, llvm::TargetMachine::getCodeModel(), getTargetTriple(), llvm::GlobalValue::getValueType(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::GlobalValue::hasExternalLinkage(), llvm::GlobalValue::hasInternalLinkage(), llvm::Type::isFunctionTy(), isTargetMachO(), isWindowsArm64EC(), llvm::CodeModel::Large, MachOUseNonLazyBind, llvm::AArch64II::MO_ARM64EC_CALLMANGLE, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NO_FLAG, and llvm::TargetMachine::shouldAssumeDSOLocal().

◆ ClassifyGlobalReference()

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget.

Find the target operand flags that describe how a global value should be referenced for the current subtarget.

Definition at line 438 of file AArch64Subtarget.cpp.

References llvm::TargetMachine::getCodeModel(), getTargetTriple(), llvm::GlobalValue::getValueType(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::GlobalValue::hasExternalWeakLinkage(), llvm::isa(), llvm::GlobalValue::isTagged(), isTargetMachO(), llvm::CodeModel::Large, llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_NO_FLAG, llvm::AArch64II::MO_TAGGED, llvm::TargetMachine::shouldAssumeDSOLocal(), llvm::CodeModel::Tiny, and useSmallAddressing().

Referenced by classifyGlobalFunctionReference(), and performGlobalAddressCombine().

◆ enableEarlyIfConversion()

bool AArch64Subtarget::enableEarlyIfConversion ( ) const	override

◆ enableMachinePipeliner()

bool AArch64Subtarget::enableMachinePipeliner ( ) const	override

◆ enableMachineScheduler()

bool llvm::AArch64Subtarget::enableMachineScheduler ( ) const	inlineoverride

◆ enablePostRAScheduler()

bool llvm::AArch64Subtarget::enablePostRAScheduler ( ) const	inlineoverride

◆ enableSubRegLiveness()

bool llvm::AArch64Subtarget::enableSubRegLiveness ( ) const	inlineoverride

◆ getAuthenticatedLRCheckMethod()

◆ getCacheLineSize()

unsigned llvm::AArch64Subtarget::getCacheLineSize ( ) const	inlineoverride

◆ getCallLowering()

◆ getChkStkName()

const char * llvm::AArch64Subtarget::getChkStkName ( ) const	inline

◆ getCustomPBQPConstraints()

std::unique_ptr< PBQPRAConstraint > AArch64Subtarget::getCustomPBQPConstraints ( ) const	override

◆ getEpilogueVectorizationMinVF()

unsigned llvm::AArch64Subtarget::getEpilogueVectorizationMinVF ( ) const	inline

◆ getFrameLowering()

◆ getGatherOverhead()

unsigned llvm::AArch64Subtarget::getGatherOverhead ( ) const	inline

◆ getInlineAsmLowering()

◆ getInstrInfo()

◆ getInstructionSelector()

◆ getLegalizerInfo()

◆ getMaxBytesForLoopAlignment()

unsigned llvm::AArch64Subtarget::getMaxBytesForLoopAlignment ( ) const	inline

◆ getMaximumJumpTableSize()

unsigned llvm::AArch64Subtarget::getMaximumJumpTableSize ( ) const	inline

◆ getMaxInterleaveFactor()

unsigned llvm::AArch64Subtarget::getMaxInterleaveFactor ( ) const	inline

◆ getMaxPrefetchIterationsAhead()

unsigned llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead ( ) const	inlineoverride

◆ getMaxSVEVectorSizeInBits()

unsigned llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits ( ) const	inline

◆ getMinimumJumpTableEntries()

unsigned llvm::AArch64Subtarget::getMinimumJumpTableEntries ( ) const	inline

◆ getMinPrefetchStride()

◆ getMinSVEVectorSizeInBits()

unsigned llvm::AArch64Subtarget::getMinSVEVectorSizeInBits ( ) const	inline

◆ getMinVectorRegisterBitWidth()

unsigned llvm::AArch64Subtarget::getMinVectorRegisterBitWidth ( ) const	inline

◆ getNumXRegisterReserved()

unsigned llvm::AArch64Subtarget::getNumXRegisterReserved ( ) const	inline

◆ getPrefetchDistance()

unsigned llvm::AArch64Subtarget::getPrefetchDistance ( ) const	inlineoverride

◆ getPrefFunctionAlignment()

Align llvm::AArch64Subtarget::getPrefFunctionAlignment ( ) const	inline

◆ getPrefLoopAlignment()

Align llvm::AArch64Subtarget::getPrefLoopAlignment ( ) const	inline

◆ getProcFamily()

ARMProcFamilyEnum llvm::AArch64Subtarget::getProcFamily ( ) const	inline

◆ getPtrAuthBlockAddressDiscriminatorIfEnabled()

std::optional< uint16_t > AArch64Subtarget::getPtrAuthBlockAddressDiscriminatorIfEnabled	(	const Function &	ParentFn	)	const

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getScatterOverhead()

unsigned llvm::AArch64Subtarget::getScatterOverhead ( ) const	inline

◆ getSelectionDAGInfo()

◆ getStreamingHazardSize()

unsigned llvm::AArch64Subtarget::getStreamingHazardSize ( ) const	inline

Returns the size of memory region that if accessed by both the CPU and the SME unit could result in a hazard.

0 = disabled.

Definition at line 197 of file AArch64Subtarget.h.

References StreamingHazardSize.

◆ getSVETailFoldingDefaultOpts()

TailFoldingOpts llvm::AArch64Subtarget::getSVETailFoldingDefaultOpts ( ) const	inline

◆ getSVEVectorSizeInBits()

unsigned llvm::AArch64Subtarget::getSVEVectorSizeInBits ( ) const	inline

◆ getTargetLowering()

◆ getTargetTriple()

const Triple & llvm::AArch64Subtarget::getTargetTriple ( ) const	inline

◆ getVectorInsertExtractBaseCost()

unsigned AArch64Subtarget::getVectorInsertExtractBaseCost	(	)	const

◆ getVScaleForTuning()

unsigned llvm::AArch64Subtarget::getVScaleForTuning ( ) const	inline

◆ hasCustomCallingConv()

bool llvm::AArch64Subtarget::hasCustomCallingConv ( ) const	inline

◆ hasFusion()

bool llvm::AArch64Subtarget::hasFusion ( ) const	inline

Return true if the CPU supports any kind of instruction fusion.

Definition at line 260 of file AArch64Subtarget.h.

◆ isAppleMLike()

bool llvm::AArch64Subtarget::isAppleMLike ( ) const	inline

◆ isCallingConvWin64()

◆ isLittleEndian()

bool llvm::AArch64Subtarget::isLittleEndian ( ) const	inline

◆ isLRReservedForRA()

bool llvm::AArch64Subtarget::isLRReservedForRA ( ) const	inline

◆ isNeonAvailable()

bool llvm::AArch64Subtarget::isNeonAvailable ( ) const	inline

Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e.g.

the function is known not to be in streaming-SVE mode, which disables NEON instructions).

Definition at line 205 of file AArch64Subtarget.h.

References isStreaming(), and isStreamingCompatible().

Referenced by llvm::AArch64FrameLowering::canUseRedZone(), GenerateFixedLengthSVETBL(), getMinVectorRegisterBitWidth(), isEligibleForSmallVectorLoadOpt(), performBuildVectorCombine(), performFpToIntCombine(), performIntToFpCombine(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), useSVEForFixedLengthVectors(), and useSVEForFixedLengthVectors().

◆ isNonStreamingSVEorSME2Available()

bool llvm::AArch64Subtarget::isNonStreamingSVEorSME2Available ( ) const	inline

◆ isStreaming()

bool llvm::AArch64Subtarget::isStreaming ( ) const	inline

◆ isStreamingCompatible()

bool llvm::AArch64Subtarget::isStreamingCompatible ( ) const	inline

◆ isStreamingSVEAvailable()

bool llvm::AArch64Subtarget::isStreamingSVEAvailable ( ) const	inline

◆ isSVEAvailable()

bool llvm::AArch64Subtarget::isSVEAvailable ( ) const	inline

◆ isSVEorStreamingSVEAvailable()

bool llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable ( ) const	inline

◆ isTargetAndroid()

bool llvm::AArch64Subtarget::isTargetAndroid ( ) const	inline

◆ isTargetCOFF()

bool llvm::AArch64Subtarget::isTargetCOFF ( ) const	inline

◆ isTargetDarwin()

bool llvm::AArch64Subtarget::isTargetDarwin ( ) const	inline

◆ isTargetELF()

bool llvm::AArch64Subtarget::isTargetELF ( ) const	inline

◆ isTargetFuchsia()

bool llvm::AArch64Subtarget::isTargetFuchsia ( ) const	inline

◆ isTargetILP32()

bool llvm::AArch64Subtarget::isTargetILP32 ( ) const	inline

◆ isTargetIOS()

bool llvm::AArch64Subtarget::isTargetIOS ( ) const	inline

◆ isTargetLinux()

bool llvm::AArch64Subtarget::isTargetLinux ( ) const	inline

◆ isTargetMachO()

bool llvm::AArch64Subtarget::isTargetMachO ( ) const	inline

◆ isTargetWindows()

bool llvm::AArch64Subtarget::isTargetWindows ( ) const	inline

◆ isWindowsArm64EC()

bool llvm::AArch64Subtarget::isWindowsArm64EC ( ) const	inline

◆ isX16X17Safer()

bool AArch64Subtarget::isX16X17Safer	(	)	const

Returns whether the operating system makes it safer to store sensitive values in x16 and x17 as opposed to other registers.

Definition at line 646 of file AArch64Subtarget.cpp.

References isTargetDarwin().

◆ isXRaySupported()

bool llvm::AArch64Subtarget::isXRaySupported ( ) const	inlineoverride

◆ isXRegCustomCalleeSaved()

bool llvm::AArch64Subtarget::isXRegCustomCalleeSaved ( size_t i) const	inline

◆ isXRegisterReserved()

bool llvm::AArch64Subtarget::isXRegisterReserved ( size_t i) const	inline

◆ isXRegisterReservedForRA()

bool llvm::AArch64Subtarget::isXRegisterReservedForRA ( size_t i) const	inline

◆ mirFileLoaded()

void AArch64Subtarget::mirFileLoaded ( MachineFunction & MF) const	override

◆ overrideSchedPolicy()

◆ ParseSubtargetFeatures()

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

◆ supportsAddressTopByteIgnored()

bool AArch64Subtarget::supportsAddressTopByteIgnored	(	)	const

◆ swiftAsyncContextIsDynamicallySet()

bool llvm::AArch64Subtarget::swiftAsyncContextIsDynamicallySet ( ) const	inline

◆ useAA()

bool AArch64Subtarget::useAA ( ) const	override

◆ useDFAforSMS()

bool llvm::AArch64Subtarget::useDFAforSMS ( ) const	inlineoverride

◆ useScalarIncVL()

bool AArch64Subtarget::useScalarIncVL	(	)	const

◆ useSmallAddressing()

bool llvm::AArch64Subtarget::useSmallAddressing ( ) const	inline

◆ useSVEForFixedLengthVectors() [1/2]

bool llvm::AArch64Subtarget::useSVEForFixedLengthVectors ( ) const	inline

◆ useSVEForFixedLengthVectors() [2/2]

bool llvm::AArch64Subtarget::useSVEForFixedLengthVectors ( EVT VT) const	inline

◆ ARMProcFamily

ARMProcFamilyEnum llvm::AArch64Subtarget::ARMProcFamily = Generic	protected

◆ CacheLineSize

uint16_t llvm::AArch64Subtarget::CacheLineSize = 0	protected

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::AArch64Subtarget::CallLoweringInfo	protected

◆ CustomCallSavedXRegs

BitVector llvm::AArch64Subtarget::CustomCallSavedXRegs	protected

◆ DefaultSVETFOpts

◆ EnableSubregLiveness

bool llvm::AArch64Subtarget::EnableSubregLiveness	protected

◆ EpilogueVectorizationMinVF

unsigned llvm::AArch64Subtarget::EpilogueVectorizationMinVF = 16	protected

◆ FrameLowering

◆ GatherOverhead

unsigned llvm::AArch64Subtarget::GatherOverhead = 10	protected

◆ InlineAsmLoweringInfo

◆ InstrInfo

◆ InstSelector

◆ IsLittle

bool llvm::AArch64Subtarget::IsLittle	protected

◆ IsStreaming

bool llvm::AArch64Subtarget::IsStreaming	protected

◆ IsStreamingCompatible

bool llvm::AArch64Subtarget::IsStreamingCompatible	protected

◆ Legalizer

◆ MaxBytesForLoopAlignment

unsigned llvm::AArch64Subtarget::MaxBytesForLoopAlignment = 0	protected

◆ MaxInterleaveFactor

uint8_t llvm::AArch64Subtarget::MaxInterleaveFactor = 2	protected

◆ MaxJumpTableSize

unsigned llvm::AArch64Subtarget::MaxJumpTableSize = 0	protected

◆ MaxPrefetchIterationsAhead

unsigned llvm::AArch64Subtarget::MaxPrefetchIterationsAhead = UINT_MAX	protected

◆ MaxSVEVectorSizeInBits

unsigned llvm::AArch64Subtarget::MaxSVEVectorSizeInBits	protected

◆ MinimumJumpTableEntries

unsigned llvm::AArch64Subtarget::MinimumJumpTableEntries = 4	protected

◆ MinPrefetchStride

uint16_t llvm::AArch64Subtarget::MinPrefetchStride = 1	protected

◆ MinSVEVectorSizeInBits

unsigned llvm::AArch64Subtarget::MinSVEVectorSizeInBits	protected

◆ MinVectorRegisterBitWidth

unsigned llvm::AArch64Subtarget::MinVectorRegisterBitWidth = 64	protected

◆ PrefetchDistance

uint16_t llvm::AArch64Subtarget::PrefetchDistance = 0	protected

◆ PrefFunctionAlignment

Align llvm::AArch64Subtarget::PrefFunctionAlignment	protected

◆ PrefLoopAlignment

Align llvm::AArch64Subtarget::PrefLoopAlignment	protected

◆ RegBankInfo

◆ ReserveXRegister

BitVector llvm::AArch64Subtarget::ReserveXRegister	protected

◆ ReserveXRegisterForRA

BitVector llvm::AArch64Subtarget::ReserveXRegisterForRA	protected

◆ ScatterOverhead

unsigned llvm::AArch64Subtarget::ScatterOverhead = 10	protected

◆ StreamingHazardSize

std::optional<unsigned> llvm::AArch64Subtarget::StreamingHazardSize	protected

◆ TargetTriple

Triple llvm::AArch64Subtarget::TargetTriple	protected

TargetTriple - What processor and OS we're targeting.

Definition at line 97 of file AArch64Subtarget.h.

Referenced by AArch64Subtarget(), getTargetTriple(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetELF(), isTargetFuchsia(), isTargetILP32(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetWindows(), isWindowsArm64EC(), and supportsAddressTopByteIgnored().

◆ TLInfo

◆ TSInfo

◆ VectorInsertExtractBaseCost

uint8_t llvm::AArch64Subtarget::VectorInsertExtractBaseCost = 2	protected

◆ VScaleForTuning

unsigned llvm::AArch64Subtarget::VScaleForTuning = 1	protected

The documentation for this class was generated from the following files:

lib/Target/AArch64/AArch64Subtarget.h
lib/Target/AArch64/AArch64Subtarget.cpp