AMDGPUISelDAGToDAG.h Source File (original) (raw)

31 if (N.isUndef()) {

32 Out = 0;

33 return true;

34 }

37 Out = C->getAPIntValue().getSExtValue();

38 return true;

39 }

42 Out = C->getValueAPF().bitcastToAPInt().getSExtValue();

43 return true;

44 }

46 return false;

47}

61 bool fp16SrcZerosHighBits(unsigned Opc) const;

63public:

74protected:

78private:

79 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;

81 bool isInlineImmediate(const SDNode *N) const;

83 bool isInlineImmediate(const APInt &Imm) const {

84 return Subtarget->getInstrInfo()->isInlineConstant(Imm);

85 }

87 bool isInlineImmediate(const APFloat &Imm) const {

89 }

91 bool isVGPRImm(const SDNode *N) const;

92 bool isUniformLoad(const SDNode *N) const;

93 bool isUniformBr(const SDNode *N) const;

97 bool isUnneededShiftMask(const SDNode *N, unsigned ShAmtBits) const;

101

102 MachineSDNode *buildSMovImm64(SDLoc &DL, uint64_t Val, EVT VT) const;

103

104 SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG) const;

105

106 SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;

107 SDNode *glueCopyToM0(SDNode *N, SDValue Val) const;

108 SDNode *glueCopyToM0LDSInit(SDNode *N) const;

109

110 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;

114 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,

115 unsigned Size) const;

116

117 bool isFlatScratchBaseLegal(SDValue Addr) const;

118 bool isFlatScratchBaseLegalSV(SDValue Addr) const;

119 bool isFlatScratchBaseLegalSVImm(SDValue Addr) const;

120 bool isSOffsetLegalWithImmOffset(SDValue *SOffset, bool Imm32Only,

121 bool IsBuffer, int64_t ImmOffset = 0) const;

122

135 bool SelectMUBUFScratchOffen(SDNode *Parent, SDValue Addr, SDValue &RSrc,

137 SDValue &ImmOffset) const;

138 bool SelectMUBUFScratchOffset(SDNode *Parent, SDValue Addr, SDValue &SRsrc,

140

143 bool SelectBUFSOffset(SDValue Addr, SDValue &SOffset) const;

144

145 bool SelectFlatOffsetImpl(SDNode *N, SDValue Addr, SDValue &VAddr,

147 bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr,

149 bool SelectGlobalOffset(SDNode *N, SDValue Addr, SDValue &VAddr,

151 bool SelectScratchOffset(SDNode *N, SDValue Addr, SDValue &VAddr,

153 bool SelectGlobalSAddr(SDNode *N, SDValue Addr, SDValue &SAddr,

155 bool NeedIOffset = true) const;

156 bool SelectGlobalSAddr(SDNode *N, SDValue Addr, SDValue &SAddr,

159 bool SelectGlobalSAddrCPol(SDNode *N, SDValue Addr, SDValue &SAddr,

162 bool SelectGlobalSAddrCPolM0(SDNode *N, SDValue Addr, SDValue &SAddr,

165 bool SelectGlobalSAddrGLC(SDNode *N, SDValue Addr, SDValue &SAddr,

168 bool SelectGlobalSAddrNoIOffset(SDNode *N, SDValue Addr, SDValue &SAddr,

170 bool SelectGlobalSAddrNoIOffsetM0(SDNode *N, SDValue Addr, SDValue &SAddr,

172 bool SelectScratchSAddr(SDNode *N, SDValue Addr, SDValue &SAddr,

174 bool checkFlatScratchSVSSwizzleBug(SDValue VAddr, SDValue SAddr,

176 bool SelectScratchSVAddr(SDNode *N, SDValue Addr, SDValue &VAddr,

179

180 bool SelectSMRDOffset(SDNode *N, SDValue ByteOffsetNode, SDValue *SOffset,

182 bool IsBuffer = false, bool HasSOffset = false,

183 int64_t ImmOffset = 0,

184 bool *ScaleOffset = nullptr) const;

186 bool SelectSMRDBaseOffset(SDNode *N, SDValue Addr, SDValue &SBase,

188 bool Imm32Only = false, bool IsBuffer = false,

189 bool HasSOffset = false, int64_t ImmOffset = 0,

190 bool *ScaleOffset = nullptr) const;

193 bool *ScaleOffset = nullptr) const;

196 bool SelectScaleOffset(SDNode *N, SDValue &Offset, bool IsSigned) const;

199 bool SelectSMRDSgprImm(SDNode *N, SDValue Addr, SDValue &SBase,

204 bool SelectSMRDBufferSgprImm(SDValue N, SDValue &SOffset,

206 bool SelectSMRDPrefetchImm(SDValue Addr, SDValue &SBase,

209

210 bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods,

211 bool IsCanonicalizing = true,

212 bool AllowAbs = true) const;

214 bool SelectVOP3ModsNonCanonicalizing(SDValue In, SDValue &Src,

217 bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;

224

226 bool OpSel) const;

229

232

234 bool IsDOT = false) const;

236

237 bool SelectWMMAOpSelVOP3PMods(SDValue In, SDValue &Src) const;

238

239 bool SelectWMMAModsF32NegAbs(SDValue In, SDValue &Src,

242 bool SelectWMMAModsF16NegAbs(SDValue In, SDValue &Src,

244 bool SelectWMMAVISrc(SDValue In, SDValue &Src) const;

245

249

251

253 bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods,

254 MVT VT) const;

255 bool SelectVOP3PMadMixModsExt(SDValue In, SDValue &Src,

258 bool SelectVOP3PMadMixBF16ModsExt(SDValue In, SDValue &Src,

260 bool SelectVOP3PMadMixBF16Mods(SDValue In, SDValue &Src,

262

265

267

268 SDValue getMaterializedScalarImm32(int64_t Val, const SDLoc &DL) const;

269

270 void SelectADD_SUB_I64(SDNode *N);

271 void SelectAddcSubb(SDNode *N);

272 void SelectUADDO_USUBO(SDNode *N);

273 void SelectDIV_SCALE(SDNode *N);

274 void SelectMAD_64_32(SDNode *N);

275 void SelectMUL_LOHI(SDNode *N);

276 void SelectFMA_W_CHAIN(SDNode *N);

277 void SelectFMUL_W_CHAIN(SDNode *N);

280 void SelectS_BFEFromShifts(SDNode *N);

281 void SelectS_BFE(SDNode *N);

282 bool isCBranchSCC(const SDNode *N) const;

283 void SelectBRCOND(SDNode *N);

284 void SelectFMAD_FMA(SDNode *N);

285 void SelectFP_EXTEND(SDNode *N);

286 void SelectDSAppendConsume(SDNode *N, unsigned IntrID);

287 void SelectDSBvhStackIntrinsic(SDNode *N, unsigned IntrID);

288 void SelectDS_GWS(SDNode *N, unsigned IntrID);

289 void SelectInterpP1F16(SDNode *N);

290 void SelectINTRINSIC_W_CHAIN(SDNode *N);

291 void SelectINTRINSIC_WO_CHAIN(SDNode *N);

292 void SelectINTRINSIC_VOID(SDNode *N);

293 void SelectWAVE_ADDRESS(SDNode *N);

294 void SelectSTACKRESTORE(SDNode *N);

295

296protected:

297

298#include "AMDGPUGenDAGISel.inc"

299};