AMDGPUISelLowering.h Source File (original) (raw)

15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H

16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H

21namespace llvm {

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161 const EVT &LoVT, const EVT &HighVT,

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207 bool LegalOperations, bool ForCodeSize,

209 unsigned Depth) const override;

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223 bool ForCodeSize) const override;

226 std::optional ByteOffset) const override;

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232 unsigned NumElem,

233 unsigned AS) const override;

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264 int ClobberedFI) const;

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281 SDValue CC, DAGCombinerInfo &DCI) const;

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285 SDValue CC, DAGCombinerInfo &DCI) const;

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301 int &RefinementSteps, bool &UseOneConstNR,

302 bool Reciprocal) const override;

304 int &RefinementSteps) const override;

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314 const APInt &DemandedElts,

316 unsigned Depth = 0) const override;

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320 unsigned Depth = 0) const override;

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324 const APInt &DemandedElts,

326 unsigned Depth = 0) const override;

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329 const APInt &DemandedElts,

332 unsigned Depth) const override;

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336 unsigned Depth = 0) const override;

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350 bool RawReg = false) const;

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369 int64_t Offset) const;

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397 return MVT::i32;

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413#endif

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

block Block Frequency Analysis

const SmallVectorImpl< MachineOperand > & Cond

This file describes how to lower LLVM code to machine code.

static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)

SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const

Generate Min/Max node.

unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

This method can be implemented by targets that want to expose additional information about sign bits ...

SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const

EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const

Split a vector load into 2 loads of half the vector.

SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const

SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const

void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const

The SelectionDAGBuilder will automatically promote function arguments with illegal types.

SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL, SelectionDAG &DAG) const

SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const

SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const

bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const override

Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...

SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

bool shouldCombineMemoryType(EVT VT) const

SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const

Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...

SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const

SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const

bool isTruncateFree(EVT Src, EVT Dest) const override

bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override

SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const

TargetLowering::NegatibleCost getConstantNegateCost(const ConstantFPSDNode *C) const

SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, bool IsLog10, SDNodeFlags Flags) const

bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override

Return true if Op can create undef or poison from non-undef & non-poison operands.

SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue lowerFEXPUnsafeImpl(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags, bool IsExp10) const

bool isSDNodeAlwaysUniform(const SDNode *N) const override

bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override

Return true if it is profitable to move this shift by a constant amount through its operand,...

virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0

SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const

bool isFNegFree(EVT VT) const override

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...

SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const

SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const

unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override

This method can be implemented by targets that want to expose additional information about sign bits ...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const

SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const

bool isConstantCheaperToNegate(SDValue N) const

bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const override

bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override

If SNaN is false,.

static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src, SDNodeFlags Flags)

MVT getFenceOperandTy(const DataLayout &DL) const override

Return the type for operands of fence.

Definition AMDGPUISelLowering.h:396

uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const

Helper function that returns the byte offset of the given type of implicit parameter.

SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const

SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const

virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const

bool isConstantCostlierToNegate(SDValue N) const

SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const

SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const

SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const

Split a vector store into multiple scalar stores.

SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const

Emit approx-funcs appropriate lowering for exp10.

bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT, std::optional< unsigned > ByteOffset) const override

Return true if it is profitable to reduce a load to a smaller type.

SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const

SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const

Definition AMDGPUISelLowering.h:358

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const

SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const

bool isSelectSupported(SelectSupportKind) const override

bool isZExtFree(Type *Src, Type *Dest) const override

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...

SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const

SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

Definition AMDGPUISelLowering.h:241

SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const

SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const

bool mayIgnoreSignedZero(SDValue Op) const

SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const

bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...

std::pair< SDValue, SDValue > splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const

Split a vector value into two parts of types LoVT and HiVT.

AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI, const AMDGPUSubtarget &AMDGPUSTI)

SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const

SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI, SDValue N) const

SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const

bool isFAbsFree(EVT VT) const override

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...

SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const

Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...

SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const

static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)

SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override

Hooks for building estimates in place of slower divisions and square roots.

SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const

ImplicitParameter

Definition AMDGPUISelLowering.h:382

@ SHARED_BASE

Definition AMDGPUISelLowering.h:385

@ PRIVATE_BASE

Definition AMDGPUISelLowering.h:384

@ FIRST_IMPLICIT

Definition AMDGPUISelLowering.h:383

@ QUEUE_PTR

Definition AMDGPUISelLowering.h:386

static SDValue stripBitcast(SDValue Val)

Definition AMDGPUISelLowering.h:191

SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const

Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.

SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const

Split a vector store into 2 stores of half the vector.

SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const

SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...

AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

Definition AMDGPUISelLowering.h:245

std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const

Return 64-bit value Op as two 32-bit integers.

SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override

Return a reciprocal estimate value for the input operand.

SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const

Definition AMDGPUISelLowering.h:351

bool hasMultipleConditionRegisters(EVT VT) const override

Does the target have multiple (allocatable) condition registers that can be used to store the results...

Definition AMDGPUISelLowering.h:400

SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const

SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const

static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)

std::pair< SDValue, SDValue > getScaledLogInput(SelectionDAG &DAG, const SDLoc SL, SDValue Op, SDNodeFlags Flags) const

If denormal handling is required return the scaled input to FLOG2, and the check for denormal range.

static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)

Selects the correct CCAssignFn for a given CallingConvention value.

static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)

SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)

SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const

SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const

SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const

static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags)

bool ShouldShrinkFPConstant(EVT VT) const override

If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked when a node result type is illegal for the target, and the operation was reg...

SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const

SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const

SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const

static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc)

bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override

Return true if it's profitable to narrow operations of type SrcVT to DestVT.

SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const

SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const

SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const

SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const

AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override

Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.

Definition AMDGPUISelLowering.h:249

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const

SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const

Widen a suitably aligned v3 load.

bool mergeStoresAfterLegalization(EVT) const override

Allow store merging for the specified type after legalization in addition to before legalization.

Definition AMDGPUISelLowering.h:295

std::pair< EVT, EVT > getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const

Split a vector type into two parts.

SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const

bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Definition AMDGPUISelLowering.h:297

SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const

unsigned getVectorIdxWidth(const DataLayout &) const override

Returns the type to be used for the index operand vector operations.

Class for arbitrary precision integers.

an instruction that atomically reads a memory location, combines it with another value,...

CCState - This class holds information needed while lowering arguments and return values.

A parsed version of the target data layout string in and methods for querying it.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

A description of a memory reference used in the backend.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

An SDNode that represents everything that will be needed to construct a MachineInstr.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

const SDValue & getOperand(unsigned i) const

unsigned getOpcode() const

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

SelectSupportKind

Enum that describes what type of support for selects the target has.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

NegatibleCost

Enum that specifies when a float negation is beneficial.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetSubtargetInfo - Generic base class for all target subtargets.

The instances of the Type class are immutable: once they are created, they are never changed.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

LoadExtType

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

This is an optimization pass for GlobalISel generic memory operations.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

DWARFExpression::Operation Op

@ Enabled

Convert any .debug_str_offsets tables to DWARF64 if needed.

static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))

These are IR-level optimization flags that may be propagated to SDNodes.