AMDGPUMCInstLower.cpp Source File (original) (raw)

34#include

36using namespace llvm;

38#include "AMDGPUGenMCPseudoLowering.inc"

43 Ctx(ctx), ST(st), AP(ap) { }

46 switch (MOFlags) {

47 default:

63 }

64}

69 default:

70 break;

73 return true;

76 return true;

80 return true;

92 }

94 return true;

95 }

100 return true;

101 }

103

104 return false;

109 return true;

110 }

111 break;

112 }

114}

115

117 unsigned Opcode = MI->getOpcode();

119

120

121

122

123 if (Opcode == AMDGPU::S_SETPC_B64_return)

124 Opcode = AMDGPU::S_SETPC_B64;

125 else if (Opcode == AMDGPU::SI_CALL) {

126

127

128 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));

134 return;

135 } else if (Opcode == AMDGPU::SI_TCRETURN ||

136 Opcode == AMDGPU::SI_TCRETURN_GFX) {

137

138 Opcode = AMDGPU::S_SETPC_B64;

139 }

140

141 int MCOpcode = TII->pseudoToMCOpcode(Opcode);

142 if (MCOpcode == -1) {

143 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();

144 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "

145 "a target-specific version: " + Twine(MI->getOpcode()));

146 }

147

149

154 }

155

159}

160

165 return MCInstLowering.lowerOperand(MO, MCOp);

166}

167

169

170

171 if (const GlobalVariable *GV = dyn_cast(CV)) {

172 if (std::optional<uint32_t> Address =

176 }

177 }

178

180 return E;

182}

183

185

186

187

188

191 return;

192 }

193

196

199 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();

200 C.emitError("Illegal instruction detected: " + Err);

202 }

203

204 if (MI->isBundle()) {

207 while (I != MBB->instr_end() && I->isInsideBundle()) {

209 ++I;

210 }

211 } else {

212

213

214

215 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {

217 OutStreamer->emitRawComment(" return to shader part epilog");

218 return;

219 }

220

221 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {

223 OutStreamer->emitRawComment(" wave barrier");

224 return;

225 }

226

227 if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) {

229 std::string HexString;

231 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);

232 OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")");

233 }

234 return;

235 }

236

237 if (MI->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) {

239 std::string HexString;

241 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);

243 " sched_group_barrier mask(" + HexString + ") size(" +

244 Twine(MI->getOperand(1).getImm()) + ") SyncID(" +

245 Twine(MI->getOperand(2).getImm()) + ")");

246 }

247 return;

248 }

249

250 if (MI->getOpcode() == AMDGPU::IGLP_OPT) {

252 std::string HexString;

254 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);

255 OutStreamer->emitRawComment(" iglp_opt mask(" + HexString + ")");

256 }

257 return;

258 }

259

260 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {

262 OutStreamer->emitRawComment(" divergent unreachable");

263 return;

264 }

265

266 if (MI->isMetaInstruction()) {

268 OutStreamer->emitRawComment(" meta instruction");

269 return;

270 }

271

273 MCInstLowering.lower(MI, TmpInst);

275

276#ifdef EXPENSIVE_CHECKS

277

278

279

280

281

282

283

284

285 if (->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&

289

292 InstEmitter->encodeInstruction(TmpInst, CodeBytes, Fixups, STI);

293

295 }

296#endif

297

298 if (DumpCodeInstEmitter) {

299

301 std::string &DisasmLine = DisasmLines.back();

303

307

308

311

315 std::string &HexLine = HexLines.back();

317

318 for (size_t i = 0; i < CodeBytes.size(); i += 4) {

319 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];

320 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);

321 }

322

324 }

325 }

326}

AMDGPU Assembly printer class.

static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)

Header of lower AMDGPU MachineInstrs to their corresponding MCInst.

Provides AMDGPU specific target descriptions.

This file contains the declarations for the subclasses of Constant, which represent the different fla...

const HexagonInstrInfo * TII

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static SDValue lowerAddrSpaceCast(SDValue Op, SelectionDAG &DAG)

bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const

AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST, const AsmPrinter &AP)

void lower(const MachineInstr *MI, MCInst &OutMI) const

Lower a MachineInstr to an MCInst.

std::vector< std::string > DisasmLines

std::vector< std::string > HexLines

bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const

Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated pseudo lowering.

bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst)

tblgen'erated driver function for lowering simple MI->MC pseudo instructions.

const MCExpr * lowerConstant(const Constant *CV) override

Lower the specified LLVM Constant to an MCExpr.

void emitInstruction(const MachineInstr *MI) override

Implemented in AMDGPUMCInstLower.cpp.

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

static std::optional< uint32_t > getLDSAbsoluteAddress(const GlobalValue &GV)

This class is intended to be used as a driving class for all asm writers.

void EmitToStreamer(MCStreamer &S, const MCInst &Inst)

TargetMachine & TM

Target machine description.

MachineFunction * MF

The current machine function.

MCContext & OutContext

This is the context for the output file that we are streaming.

std::unique_ptr< MCStreamer > OutStreamer

This is the MCStreamer object for the file we are generating.

virtual const MCExpr * lowerConstant(const Constant *CV)

Lower the specified LLVM Constant to an MCExpr.

bool isVerbose() const

Return true if assembly output should contain comments.

void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const

This is an important base class in LLVM.

const SIInstrInfo * getInstrInfo() const override

bool hasOffset3fBug() const

const SIRegisterInfo * getRegisterInfo() const override

This is an important class for using LLVM in a threaded context.

static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0

Encode the given Inst to bytes and append to CB.

static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

MCSymbol * getOrCreateSymbol(const Twine &Name)

Lookup the symbol inside with the specified Name.

Base class for the full range of assembler expressions which are needed for parsing.

Instances of this class represent a single low-level machine instruction.

unsigned getNumOperands() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

Instances of this class represent operands of the MCInst class.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Represent a reference to a symbol from inside an expression.

@ VK_AMDGPU_GOTPCREL32_LO

@ VK_AMDGPU_GOTPCREL32_HI

static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

MCSymbol * getSymbol() const

Return the MCSymbol for this basic block.

instr_iterator instr_end()

Instructions::const_iterator const_instr_iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

const GlobalValue * getGlobal() const

MachineBasicBlock * getMBB() const

unsigned getTargetFlags() const

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

const char * getSymbolName() const

getReg - Returns the register number.

MCSymbol * getMCSymbol() const

@ MO_Immediate

Immediate operand.

@ MO_MCSymbol

MCSymbol reference (for debug/eh info)

@ MO_GlobalAddress

Address of a global value.

@ MO_RegisterMask

Mask of preserved registers.

@ MO_MachineBasicBlock

MachineBasicBlock reference.

@ MO_Register

@ MO_ExternalSymbol

Name of external global symbol.

int64_t getOffset() const

Return the offset from the symbol in this operand.

virtual void print(raw_ostream &OS, const Module *M) const

print - Print out the internal state of the pass.

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetInstrInfo * getInstrInfo() const

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

static IntegerType * getInt32Ty(LLVMContext &C)

LLVMContext & getContext() const

All values hold a context through their type.

A raw_ostream that writes to an std::string.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)

format_hex - Output N as a fixed width hexadecimal.

format_object< Ts... > format(const char *Fmt, const Ts &... Vals)

These are helper functions used to produce formatted output.

raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)