LLVM: llvm::MCSubtargetInfo Class Reference (original) (raw)

Generic base class for all target subtargets. More...

#include "[llvm/MC/MCSubtargetInfo.h](MCSubtargetInfo%5F8h%5Fsource.html)"

Public Types
enum HwModeType { HwMode_Default, HwMode_ValueType, HwMode_RegInfo, HwMode_EncodingInfo }
HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specific IDs, such as the RegInfo HwMode ID, from the set as required. More...
Public Member Functions
MCSubtargetInfo (const MCSubtargetInfo &)=default
MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
MCSubtargetInfo ()=delete
MCSubtargetInfo & operator= (const MCSubtargetInfo &)=delete
MCSubtargetInfo & operator= (MCSubtargetInfo &&)=delete
virtual ~MCSubtargetInfo ()=default
const Triple & getTargetTriple () const
StringRef getCPU () const
StringRef getTuneCPU () const
const FeatureBitset & getFeatureBits () const
void setFeatureBits (const FeatureBitset &FeatureBits_)
StringRef getFeatureString () const
bool hasFeature (unsigned Feature) const
void setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
FeatureBitset ToggleFeature (uint64_t FB)
Toggle a feature and return the re-computed feature bits.
FeatureBitset ToggleFeature (const FeatureBitset &FB)
Toggle a feature and return the re-computed feature bits.
FeatureBitset ToggleFeature (StringRef FS)
Toggle a set of features and return the re-computed feature bits.
FeatureBitset ApplyFeatureFlag (StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.
FeatureBitset SetFeatureBitsTransitively (const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
FeatureBitset ClearFeatureBitsTransitively (const FeatureBitset &FB)
bool checkFeatures (StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU (StringRef CPU) const
Get the machine model of a CPU.
const MCSchedModel & getSchedModel () const
Get the machine model for this subtarget's CPU.
const MCWriteProcResEntry * getWriteProcResBegin (const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
const MCWriteProcResEntry * getWriteProcResEnd (const MCSchedClassDesc *SC) const
const MCWriteLatencyEntry * getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries (const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
Get scheduling itinerary of a CPU.
void initInstrItins (InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
virtual unsigned resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
virtual bool isCPUStringValid (StringRef CPU) const
Check whether the CPU string is valid.
ArrayRef< SubtargetSubTypeKV > getAllProcessorDescriptions () const
Return processor descriptions.
ArrayRef< SubtargetFeatureKV > getAllProcessorFeatures () const
Return processor features.
std::vector< SubtargetFeatureKV > getEnabledProcessorFeatures () const
Return the list of processor features currently enabled.
virtual unsigned getHwModeSet () const
Return a bit set containing all HwMode IDs of the current subtarget.
virtual unsigned getHwMode (enum HwModeType type=HwMode_Default) const
HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current subtarget.
virtual std::optional< unsigned > getCacheSize (unsigned Level) const
Return the cache size in bytes for the given level of cache.
virtual std::optional< unsigned > getCacheAssociativity (unsigned Level) const
Return the cache associatvity for the given level of cache.
virtual std::optional< unsigned > getCacheLineSize (unsigned Level) const
Return the target cache line size in bytes at a given level.
virtual unsigned getCacheLineSize () const
Return the target cache line size in bytes.
virtual unsigned getPrefetchDistance () const
Return the preferred prefetch distance in terms of instructions.
virtual unsigned getMaxPrefetchIterationsAhead () const
Return the maximum prefetch distance in terms of loop iterations.
virtual bool enableWritePrefetching () const
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
virtual bool shouldPrefetchAddressSpace (unsigned AS) const

Generic base class for all target subtargets.

Definition at line 77 of file MCSubtargetInfo.h.

◆ HwModeType

HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specific IDs, such as the RegInfo HwMode ID, from the set as required.

Using this approach, various types of HwMode IDs can be added to a subtarget to manage different attributes within that subtarget, significantly enhancing the scalability and usability of HwMode. Moreover, to ensure compatibility, this method also supports controlling multiple attributes with a single HwMode ID, just as was done previously.

Enumerator
HwMode_Default
HwMode_ValueType
HwMode_RegInfo
HwMode_EncodingInfo

Definition at line 257 of file MCSubtargetInfo.h.

◆ MCSubtargetInfo() [2/3]

MCSubtargetInfo::MCSubtargetInfo ( const Triple & TT,
StringRef CPU,
StringRef TuneCPU,
StringRef FS,
ArrayRef< StringRef > PN,
ArrayRef< SubtargetFeatureKV > PF,
ArrayRef< SubtargetSubTypeKV > PD,
const MCWriteProcResEntry * WPR,
const MCWriteLatencyEntry * WL,
const MCReadAdvanceEntry * RA,
const InstrStage * IS,
const unsigned * OC,
const unsigned * FP )

◆ MCSubtargetInfo() [3/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( ) delete

◆ ~MCSubtargetInfo()

virtual llvm::MCSubtargetInfo::~MCSubtargetInfo ( ) virtualdefault

◆ ApplyFeatureFlag()

◆ checkFeatures()

◆ ClearFeatureBitsTransitively()

◆ enableWritePrefetching()

bool MCSubtargetInfo::enableWritePrefetching ( ) const virtual

Returns

True if prefetching should also be done for writes.

Definition at line 396 of file MCSubtargetInfo.cpp.

◆ getAllProcessorDescriptions()

◆ getAllProcessorFeatures()

◆ getCacheAssociativity()

std::optional< unsigned > MCSubtargetInfo::getCacheAssociativity ( unsigned Level) const virtual

Return the cache associatvity for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 379 of file MCSubtargetInfo.cpp.

◆ getCacheLineSize() [1/2]

virtual unsigned llvm::MCSubtargetInfo::getCacheLineSize ( ) const inlinevirtual

Return the target cache line size in bytes.

By default, return the line size for the bottom-most level of cache. This provides a more convenient interface for the common case where all cache levels have the same line size. Return zero if there is no cache model.

Definition at line 298 of file MCSubtargetInfo.h.

References getCacheLineSize(), and Size.

◆ getCacheLineSize() [2/2]

std::optional< unsigned > MCSubtargetInfo::getCacheLineSize ( unsigned Level) const virtual

◆ getCacheSize()

std::optional< unsigned > MCSubtargetInfo::getCacheSize ( unsigned Level) const virtual

Return the cache size in bytes for the given level of cache.

Level is zero-based, so a value of zero means the first level of cache.

Definition at line 374 of file MCSubtargetInfo.cpp.

◆ getCPU()

StringRef llvm::MCSubtargetInfo::getCPU ( ) const inline

Definition at line 112 of file MCSubtargetInfo.h.

Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::MCSchedModel::computeInstrLatency(), llvm::createHexagonAsmBackend(), llvm::createMipsAsmBackend(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::ARMTargetStreamer::emitTargetAttributes(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getArchForCPU(), llvm::Hexagon_MC::getArchSubtarget(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::Hexagon_MC::GetELFFlags(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), and llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getEnabledProcessorFeatures()

◆ getFeatureBits()

Definition at line 115 of file MCSubtargetInfo.h.

Referenced by llvm::AArch64TTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::BasicTTIImplBase< BasicTTIImpl >::areInlineCompatible(), llvm::PPCTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::AVRELFStreamer::AVRELFStreamer(), cannotInsertTailCall(), createAMDGPUMCSubtargetInfo(), createSparcMCSubtargetInfo(), llvm::CSKYTargetELFStreamer::CSKYTargetELFStreamer(), DecodeCopMemInstruction(), DecodeCoprocessor(), DecodeForVMRSandVMSR(), DecodeGPRPairRegisterClass(), DecodeHINTInstruction(), DecodeMSRMask(), DecoderGPRRegisterClass(), DecodeSETPANInstruction(), DecodeSRRegisterClass(), DecodeSystemPStateImm0_15Instruction(), DecodeSystemPStateImm0_1Instruction(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodeThumbTableBranch(), DecodeURRegisterClass(), DecodeVCVTD(), DecodeVCVTQ(), DecodeVSTRVLDR_SYSREG(), llvm::HexagonTargetStreamer::emitTargetAttributes(), llvm::RISCVTargetStreamer::emitTargetAttributes(), llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize(), llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::MCInstrInfo::getDeprecatedInfo(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), llvm::AMDGPU::IsaInfo::getVGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getWavefrontSize(), XtensaAsmParser::hasWindowed(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::ARM::isCDECoproc(), llvm::AMDGPU::isGFX12(), llvm::AMDGPU::isGFX1250(), isValidSysReg(), llvm::LoongArchTargetELFStreamer::LoongArchTargetELFStreamer(), matchAliasCondition(), PermitsD32(), llvm::RISCVInstPrinter::printCSRSystemRegister(), llvm::ARMInstPrinter::printMSRMaskOperand(), llvm::AArch64InstPrinter::printPrefetchOp(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSyslAlias(), llvm::AArch64InstPrinter::printSyspAlias(), llvm::AArch64InstPrinter::printSystemPStateField(), llvm::HexagonMCInstrInfo::requiresSlot(), and llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer().

◆ getFeatureString()

StringRef llvm::MCSubtargetInfo::getFeatureString ( ) const inline

◆ getHwMode()

virtual unsigned llvm::MCSubtargetInfo::getHwMode ( enum HwModeType type = HwMode_Default) const inlinevirtual

HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current subtarget.

It’s important to note that if the current subtarget possesses two HwMode IDs and both control a single attribute (such as RegInfo), this interface will result in an error.

Definition at line 272 of file MCSubtargetInfo.h.

References HwMode_Default.

Referenced by llvm::SDNodeInfo::verifyNode().

◆ getHwModeSet()

virtual unsigned llvm::MCSubtargetInfo::getHwModeSet ( ) const inlinevirtual

Return a bit set containing all HwMode IDs of the current subtarget.

Definition at line 266 of file MCSubtargetInfo.h.

◆ getInstrItineraryForCPU()

◆ getMaxPrefetchIterationsAhead()

unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead ( ) const virtual

Return the maximum prefetch distance in terms of loop iterations.

Definition at line 392 of file MCSubtargetInfo.cpp.

◆ getMinPrefetchStride()

Return the minimum stride necessary to trigger software prefetching.

Definition at line 400 of file MCSubtargetInfo.cpp.

◆ getPrefetchDistance()

unsigned MCSubtargetInfo::getPrefetchDistance ( ) const virtual

Return the preferred prefetch distance in terms of instructions.

Definition at line 388 of file MCSubtargetInfo.cpp.

◆ getReadAdvanceCycles()

◆ getReadAdvanceEntries()

◆ getSchedModel()

Get the machine model for this subtarget's CPU.

Definition at line 166 of file MCSubtargetInfo.h.

Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), llvm::mca::DispatchStage::DispatchStage(), emitComments(), emitLatency(), llvm::TargetSubtargetInfo::enablePostRAScheduler(), llvm::HexagonMCInstrInfo::getCVIResources(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::HexagonMCInstrInfo::getUnits(), llvm::TargetSchedModel::init(), llvm::mca::initializeUsedResources(), and initInstrItins().

◆ getSchedModelForCPU()

◆ getTargetTriple()

const Triple & llvm::MCSubtargetInfo::getTargetTriple ( ) const inline

Definition at line 111 of file MCSubtargetInfo.h.

Referenced by llvm::Hexagon_MC::addArchSubtarget(), llvm::ARMAsmBackend::adjustFixupValue(), llvm::createAArch64beAsmBackend(), llvm::createAArch64leAsmBackend(), llvm::createAArch64ObjectTargetStreamer(), llvm::createAMDGPUAsmBackend(), createARMAsmBackend(), llvm::createARMObjectTargetStreamer(), createAsmBackend(), llvm::createAVRAsmBackend(), createCSKYObjectTargetStreamer(), llvm::createHexagonAsmBackend(), llvm::createLanaiAsmBackend(), llvm::createLoongArchAsmBackend(), createLoongArchObjectTargetStreamer(), llvm::createM68kAsmBackend(), llvm::createMipsAsmBackend(), createMipsObjectTargetStreamer(), llvm::createMSP430ObjectTargetStreamer(), createObjectTargetStreamer(), llvm::createPPCAsmBackend(), llvm::createRISCVAsmBackend(), createRISCVObjectTargetStreamer(), llvm::createSparcAsmBackend(), llvm::createSystemZMCAsmBackend(), llvm::createVEAsmBackend(), llvm::createX86_32AsmBackend(), llvm::createX86_64AsmBackend(), llvm::createX86ObjectTargetStreamer(), llvm::createXtensaAsmBackend(), llvm::AMDGPUAsmPrinter::doFinalization(), llvm::X86_MC::X86MCInstrAnalysis::findPltEntries(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::getMCReg(), llvm::PPCMCCodeEmitter::getTLSRegEncoding(), llvm::AMDGPU::isHsaAbi(), llvm::LoongArchTargetELFStreamer::LoongArchTargetELFStreamer(), lowerMSASplatZExt(), llvm::SparcInstPrinter::printCTILabel(), llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer(), llvm::AMDGPUResourceUsageAnalysis::run(), and truncateVecElts().

◆ getTuneCPU()

StringRef llvm::MCSubtargetInfo::getTuneCPU ( ) const inline

◆ getWriteLatencyEntry()

◆ getWriteProcResBegin()

◆ getWriteProcResEnd()

◆ hasFeature()

bool llvm::MCSubtargetInfo::hasFeature ( unsigned Feature) const inline

Definition at line 122 of file MCSubtargetInfo.h.

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), adjust::adjustRelativeBranch(), checkFeature(), clearFeature(), createAMDGPUMCSubtargetInfo(), createSparcMCSubtargetInfo(), decodeFPUV3Instruction(), DecodeGPRF16RegisterClass(), DecodeGPRF32RegisterClass(), DecodeGPRRegisterClass(), decodeUImmLog2XLenOperand(), decodeZcmpRlist(), llvm::ARMTargetStreamer::emitTargetAttributes(), llvm::RISCVTargetStreamer::emitTargetAttributes(), llvm::RISCVMatInt::generateInstSeq(), generateInstSeqImpl(), generateInstSeqLeadingZeros(), llvm::RISCVMatInt::generateTwoRegInstSeq(), getArchForCPU(), getARMLoadDeprecationInfo(), getARMStoreDeprecationInfo(), getEFlagsForFeatureSet(), llvm::RISCVMatInt::getIntMatCost(), getLit16Encoding(), getLit32Encoding(), getLit64Encoding(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), getMCRDeprecationInfo(), getMRCDeprecationInfo(), getRelaxedOpcode(), llvm::ARMAsmBackend::getRelaxedOpcode(), llvm::RISCVMCObjectFileInfo::getTextSectionAlignment(), llvm::AMDGPU::hasA16(), llvm::AMDGPU::hasArchitectedFlatScratch(), llvm::AMDGPU::hasDPPSrc1SGPR(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasGDS(), llvm::AMDGPU::hasGFX10_3Insts(), llvm::AMDGPU::hasKernargPreload(), llvm::AMDGPU::hasMAIInsts(), llvm::AMDGPU::hasMIMG_R128(), llvm::ARMAsmBackend::hasNOP(), llvm::AMDGPU::hasPackedD16(), llvm::AMDGPU::hasSRAMECC(), llvm::AMDGPU::hasVOPD(), llvm::AMDGPU::hasXNACK(), llvm::ARMElfTargetObjectFile::Initialize(), llvm::X86_MC::is16BitMemOperand(), llvm::AMDGPU::isCI(), llvm::AMDGPU::isGCN3Encoding(), llvm::AMDGPU::isGFX10(), llvm::AMDGPU::isGFX10_AEncoding(), llvm::AMDGPU::isGFX10_BEncoding(), llvm::AMDGPU::isGFX11(), llvm::AMDGPU::isGFX9(), llvm::AMDGPU::isGFX90A(), llvm::AMDGPU::isGFX940(), isMicroMips(), isMips32r6(), llvm::AMDGPU::isSI(), isThumb(), isV8M(), llvm::SparcInstPrinter::isV9(), isValidInsnFormat(), llvm::AMDGPU::isVI(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::CSKYAsmBackend::mayNeedRelaxation(), llvm::MSP430TargetELFStreamer::MSP430TargetELFStreamer(), llvm::X86_MC::needsAddressSizeOverride(), llvm::HexagonMCInstrInfo::packetSizeSlots(), llvm::RISCVInstPrinter::printBranchOperand(), printImmediateBFloat16(), printImmediateFP16(), llvm::AArch64InstPrinter::printInst(), llvm::PPCInstPrinter::printInst(), llvm::X86ATTInstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::X86InstPrinterCommon::printInstFlags(), llvm::ARMInstPrinter::printMemBOption(), llvm::CSKYInstPrinter::printOperand(), llvm::RISCVInstPrinter::printStackAdj(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSyspAlias(), llvm::RISCVInstPrinter::printVTypeI(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVTargetStreamer::setFlagsFromFeatures(), and llvm::ARMAsmBackend::writeNopData().

◆ initInstrItins()

◆ InitMCProcessorInfo()

◆ isCPUStringValid()

virtual bool llvm::MCSubtargetInfo::isCPUStringValid ( StringRef CPU) const inlinevirtual

◆ operator=() [1/2]

References MCSubtargetInfo().

◆ operator=() [2/2]

References MCSubtargetInfo().

◆ resolveVariantSchedClass()

◆ setDefaultFeatures()

◆ setFeatureBits()

◆ SetFeatureBitsTransitively()

◆ shouldPrefetchAddressSpace()

bool MCSubtargetInfo::shouldPrefetchAddressSpace ( unsigned AS) const virtual

Returns

if target want to issue a prefetch in address space AS.

Definition at line 407 of file MCSubtargetInfo.cpp.

◆ ToggleFeature() [1/3]

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 267 of file MCSubtargetInfo.cpp.

◆ ToggleFeature() [2/3]

◆ ToggleFeature() [3/3]

The documentation for this class was generated from the following files: