AMDGPURegBankSelect.cpp Source File (original) (raw)

27#define DEBUG_TYPE "amdgpu-regbankselect"

29using namespace llvm;

30using namespace AMDGPU;

32namespace {

35public:

36 static char ID;

42 StringRef getPassName() const override {

43 return "AMDGPU Register Bank Select";

44 }

46 void getAnalysisUsage(AnalysisUsage &AU) const override {

51 }

57 }

58};

60}

63 "AMDGPU Register Bank Select", false, false)

70char AMDGPURegBankSelect::ID = 0;

75 return new AMDGPURegBankSelect();

76}

88public:

93 : B(B), MRI(*B.getMRI()), ILMA(ILMA), MUI(MUI), TRI(TRI),

94 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),

95 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),

96 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}

100

101

102

103

106 if (->isCopy() || MI->getNumImplicitOperands() != 1)

107 return false;

108

109 return MI->implicit_operands().begin()->getReg() == TRI.getExec();

110 }

111

114 (MUI.isUniform(Reg) || ILMA.isS32S64LaneMask(Reg)))

115 return SgprRB;

117 return VccRB;

118 return VgprRB;

119 }

120

121

122

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128

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133

134

136 LLT Ty = MRI.getType(Reg);

137 Register NewReg = MRI.createVirtualRegister({RB, Ty});

138 DefOP.setReg(NewReg);

139

140 auto &MBB = *MI.getParent();

141 B.setInsertPt(MBB, MBB.SkipPHIsAndLabels(std::next(MI.getIterator())));

142 B.buildCopy(Reg, NewReg);

143

144

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152

153

155 if (UseMI.isPreISelOpcode()) {

157 if (Op.isReg() && Op.getReg() == Reg)

158 Op.setReg(NewReg);

159 }

160 }

161 }

162 }

163

164

165

166

167

171

172 LLT Ty = MRI.getType(Reg);

173 Register NewReg = MRI.createVirtualRegister({RB, Ty});

174 UseOP.setReg(NewReg);

175

176 if (MI.isPHI()) {

177 auto DefMI = MRI.getVRegDef(Reg)->getIterator();

180 } else {

181 B.setInstr(MI);

182 }

183

184 B.buildCopy(NewReg, Reg);

185 }

186};

187

189 if (.isReg())

190 return {};

191

192

194 if ( Reg .isVirtual())

195 return {};

196

197 return Reg;

198}

199

200bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {

202 return false;

203

204

205 const TargetPassConfig &TPC = getAnalysis();

206 GISelCSEAnalysisWrapper &Wrapper =

207 getAnalysis().getCSEWrapper();

209 GISelObserverWrapper Observer;

211

212 CSEMIRBuilder B(MF);

213 B.setCSEInfo(&CSEInfo);

214 B.setChangeObserver(Observer);

215

216 RAIIDelegateInstaller DelegateInstaller(MF, &Observer);

217 RAIIMFObserverInstaller MFObserverInstaller(MF, Observer);

218

219 IntrinsicLaneMaskAnalyzer ILMA(MF);

221 getAnalysis().getUniformityInfo();

222 MachineRegisterInfo &MRI = *B.getMRI();

223 const GCNSubtarget &ST = MF.getSubtarget();

224 RegBankSelectHelper RBSHelper(B, ILMA, MUI, *ST.getRegisterInfo(),

225 *ST.getRegBankInfo());

226

227

228

229

230 for (MachineBasicBlock &MBB : MF) {

231 for (MachineInstr &MI : MBB) {

232

233

234 if (MI.isCopy()) {

236 if (!DefReg.isValid() || MRI.getRegClassOrNull(DefReg))

237 continue;

238

239 assert( MRI .getRegBankOrNull(DefReg));

240 MRI.setRegBank(DefReg, *RBSHelper.getRegBankToAssign(DefReg));

241 continue;

242 }

243

244 if (.isPreISelOpcode())

245 continue;

246

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256

257 for (MachineOperand &DefOP : MI.defs()) {

260 continue;

261

262 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg);

263 if (MRI.getRegClassOrNull(DefReg))

264 RBSHelper.reAssignRegBankOnDef(MI, DefOP, RB);

265 else {

266 assert( MRI .getRegBankOrNull(DefReg));

267 MRI.setRegBank(DefReg, *RB);

268 }

269 }

270

271

272

273 for (MachineOperand &UseOP : MI.uses()) {

276 continue;

277

278

279 if ( MRI .getRegClassOrNull(UseReg) ||

280 MRI.getVRegDef(UseReg)->isPreISelOpcode())

281 continue;

282

283

284 const RegisterBank *RB = RBSHelper.getRegBankToAssign(UseReg);

285 RBSHelper.constrainRegBankUse(MI, UseOP, RB);

286 }

287 }

288 }

289

290 return true;

291}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

amdgpu aa AMDGPU Address space based Alias Analysis Wrapper

static Register getVReg(MachineOperand &Op)

Definition AMDGPURegBankSelect.cpp:188

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Provides analysis for continuously CSEing during GISel passes.

This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.

AMD GCN specific subclass of TargetSubtarget.

static Register UseReg(const MachineOperand &MO)

Machine IR instance of the generic uniformity analysis.

Promote Memory to Register

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Target-Independent Code Generator Pass Configuration Options pass.

const RegisterBank * getRegBankToAssign(Register Reg)

Definition AMDGPURegBankSelect.cpp:112

void reAssignRegBankOnDef(MachineInstr &MI, MachineOperand &DefOP, const RegisterBank *RB)

Definition AMDGPURegBankSelect.cpp:129

RegBankSelectHelper(MachineIRBuilder &B, AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA, const MachineUniformityInfo &MUI, const SIRegisterInfo &TRI, const RegisterBankInfo &RBI)

Definition AMDGPURegBankSelect.cpp:89

bool isTemporalDivergenceCopy(Register Reg)

Definition AMDGPURegBankSelect.cpp:104

void constrainRegBankUse(MachineInstr &MI, MachineOperand &UseOP, const RegisterBank *RB)

Definition AMDGPURegBankSelect.cpp:168

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

FunctionPass class - This class is used to implement most global optimizations.

The actual analysis pass wrapper.

void addObserver(GISelChangeObserver *O)

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

LLVM_ABI iterator SkipPHIsAndLabels(iterator I)

Return the first instruction in MBB after I that is not a PHI or a label.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const MachineFunctionProperties & getProperties() const

Get the function properties.

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Legacy analysis pass which computes a MachineUniformityInfo.

Holds all the information related to register banks.

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

constexpr bool isValid() const

StringRef - Represent a constant reference to a string, i.e.

Target-Independent Code Generator Pass Configuration Options.

virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const

Returns the CSEConfig object to use for the current optimization level.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

GenericUniformityInfo< MachineSSAContext > MachineUniformityInfo

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

char & AMDGPURegBankSelectID

Definition AMDGPURegBankSelect.cpp:72

FunctionPass * createAMDGPURegBankSelectPass()

Definition AMDGPURegBankSelect.cpp:74

DWARFExpression::Operation Op