LLVM: lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h Source File (original) (raw)
1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
15
21#include
22
23namespace llvm {
24
25
36
41
43
45 switch (Op) {
53 }
54 }
55
57 switch (Op) {
63 }
64 }
65
73
75 switch (Mode) {
81 }
82 }
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
99 return ShOp | (Imm << 3);
100 }
103
104
105
106 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; }
107
108
109 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; }
110
111
112
113
114
116
117
118 if ((Imm & ~255U) == 0) return 0;
119
120
122
123
124
125 unsigned RotAmt = TZ & ~1;
126
127
129 return (32-RotAmt)&31;
130
131
132
133 if (Imm & 63U) {
135 unsigned RotAmt2 = TZ2 & ~1;
137 return (32-RotAmt2)&31;
138 }
139
140
141
142
143 return (32-RotAmt)&31;
144 }
145
146
147
148
150
151
152 if ((Arg & ~255U) == 0) return Arg;
153
155
156
158 return -1;
159
160
162 }
163
164
165
167
169 if (V == 0)
170 return false;
171
172
174 return V == 0;
175 }
176
177
178
182
183
184
186
188
189
191 return V;
192 }
193
194
195
196
197
201 return false;
202
206 }
207
208
209
211
212
213 if ((Imm & ~255U) == 0) return 0;
214
215
217 }
218
219
220
222
224 return V == 0;
225 }
226
227
228
230
231
232 if ((Imm & ~65535U) == 0) return 0;
233
234
236 }
237
238
239
241
243 return V == 0;
244 }
245
246
247
251
252
253
254
255
256
257
258
259
260
261
263 unsigned u, Vs, Imm;
264
265 if ((V & 0xffffff00) == 0)
266 return V;
267
268
269 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
270
271 Imm = Vs & 0xff;
272
273 u = Imm | (Imm << 16);
274
275
276 if (Vs == u)
277 return (((Vs == V) ? 1 : 2) << 8) | Imm;
278
279
280 if (Vs == (u | (u << 8)))
281 return (3 << 8) | Imm;
282
283 return -1;
284 }
285
286
287
288
289
292 if (RotAmt >= 24)
293 return -1;
294
295
298 ((RotAmt + 8) << 7);
299
300 return -1;
301 }
302
303
304
305
306
308
312
313
315 if (Rot != -1)
316 return Rot;
317
318 return -1;
319 }
320
322 if ((V & ~255U) == 0) return 0;
323
325 return (32 - RotAmt) & 31;
326 }
327
329 unsigned V = Imm;
330
331
332
334 return false;
336 if (V == 0)
337 return false;
338
339
341
342
343 V = Imm;
345 V &= ~0xff00ff00U;
347 V &= ~0x00ff00ffU;
348
350
351
352 return false;
353 }
354
357 "Immedate cannot be encoded as two part immediate!");
358
360
362
363
365 return Imm & 0xff00ff00U;
366
367
369 return Imm & 0x00ff00ffU;
370 }
371
373
375
377 "Unable to encode second part of T2 two part SO immediate");
378 return Imm;
379 }
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
401 unsigned IdxMode = 0) {
402 assert(Imm12 < (1 << 12) && "Imm too large!");
404 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
405 }
407 return AM2Opc & ((1 << 12)-1);
408 }
410 return ((AM2Opc >> 12) & 1) ? sub : add;
411 }
413 return (ShiftOpc)((AM2Opc >> 13) & 7);
414 }
415 inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); }
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
433 unsigned IdxMode = 0) {
435 return ((int)isSub << 8) | Offset | (IdxMode << 9);
436 }
437 inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; }
439 return ((AM3Opc >> 8) & 1) ? sub : add;
440 }
441 inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); }
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
461
463
464
465
466
467
468
469
470
471
472
473
474
475
478 return ((int)isSub << 8) | Offset;
479 }
480 inline unsigned char getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; }
482 return ((AM5Opc >> 8) & 1) ? sub : add;
483 }
484
485
486
487
488
489
490
491
492
493
494
495
496
499 return ((int)isSub << 8) | Offset;
500 }
502 return AM5Opc & 0xFF;
503 }
505 return ((AM5Opc >> 8) & 1) ? sub : add;
506 }
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
534 return (OpCmode << 8) | Val;
535 }
537 return (ModImm >> 8) & 0x1f;
538 }
539 inline unsigned getVMOVModImmVal(unsigned ModImm) { return ModImm & 0xff; }
540
541
542
543
548
549 if (OpCmode == 0xe) {
550
551 Val = Imm8;
552 EltBits = 8;
553 } else if ((OpCmode & 0xc) == 0x8) {
554
555 unsigned ByteNum = (OpCmode & 0x6) >> 1;
556 Val = Imm8 << (8 * ByteNum);
557 EltBits = 16;
558 } else if ((OpCmode & 0x8) == 0) {
559
560 unsigned ByteNum = (OpCmode & 0x6) >> 1;
561 Val = Imm8 << (8 * ByteNum);
562 EltBits = 32;
563 } else if ((OpCmode & 0xe) == 0xc) {
564
565 unsigned ByteNum = 1 + (OpCmode & 0x1);
566 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
567 EltBits = 32;
568 } else if (OpCmode == 0x1e) {
569
570 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
571 if ((ModImm >> ByteNum) & 1)
572 Val |= (uint64_t)0xff << (8 * ByteNum);
573 }
574 EltBits = 64;
575 } else {
577 }
578 return Val;
579 }
580
581
584 unsigned count = 0;
585 for (unsigned i = 0; i < Size; ++i) {
588 }
589 return count == 1;
590 }
591
592
594 if (Value > 0xffff)
595 return false;
596
598 }
599
600
603 if (Value >= 0x100)
605 else
608 }
609
610
615
616
619 if (Value >= 0x100 && Value <= 0xff00)
621 else if (Value > 0xffff && Value <= 0xff0000)
623 else if (Value > 0xffffff)
626 }
627
628
629
630
632
633
634 uint8_t Sign = (Imm >> 7) & 0x1;
635 uint8_t Exp = (Imm >> 4) & 0x7;
636 uint8_t Mantissa = Imm & 0xf;
637
638
639
640
641
643 I |= Sign << 31;
644 I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
645 I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
646 I |= (Exp & 0x3) << 23;
647 I |= Mantissa << 19;
649 }
650
651
652
653
655 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
656 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15;
657 int64_t Mantissa = Imm.getZExtValue() & 0x3ff;
658
659
660
661 if (Mantissa & 0x3f)
662 return -1;
663 Mantissa >>= 6;
664
665
666 if (Exp < -3 || Exp > 4)
667 return -1;
668 Exp = ((Exp+3) & 0x7) ^ 4;
669
670 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
671 }
672
676
677
678
680 if (Imm.getActiveBits() > 16)
681 return -1;
683 }
684
688
689
690
691
693 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
694 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127;
695 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff;
696
697
698
699 if (Mantissa & 0x7ffff)
700 return -1;
701 Mantissa >>= 19;
702 if ((Mantissa & 0xf) != Mantissa)
703 return -1;
704
705
706 if (Exp < -3 || Exp > 4)
707 return -1;
708 Exp = ((Exp+3) & 0x7) ^ 4;
709
710 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
711 }
712
716
717
718
719
721 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
722 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023;
723 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
724
725
726
727 if (Mantissa & 0xffffffffffffULL)
728 return -1;
729 Mantissa >>= 48;
730 if ((Mantissa & 0xf) != Mantissa)
731 return -1;
732
733
734 if (Exp < -3 || Exp > 4)
735 return -1;
736 Exp = ((Exp+3) & 0x7) ^ 4;
737
738 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
739 }
740
744
745}
746}
747
748#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file implements the C++20 header.
APInt bitcastToAPInt() const
Class for arbitrary precision integers.
StringRef - Represent a constant reference to a string, i.e.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ARM_AM - ARM Addressing Mode Stuff.
unsigned char getAM3Offset(unsigned AM3Opc)
Definition ARMAddressingModes.h:437
unsigned char getAM5FP16Offset(unsigned AM5Opc)
Definition ARMAddressingModes.h:501
unsigned getSORegOffset(unsigned Op)
Definition ARMAddressingModes.h:101
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
Definition ARMAddressingModes.h:149
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
Definition ARMAddressingModes.h:412
int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
Definition ARMAddressingModes.h:692
uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...
Definition ARMAddressingModes.h:544
unsigned getAM2IdxMode(unsigned AM2Opc)
Definition ARMAddressingModes.h:415
unsigned getT2SOImmValRotate(unsigned V)
Definition ARMAddressingModes.h:321
unsigned encodeNEONi16splat(unsigned Value)
Definition ARMAddressingModes.h:601
unsigned getAM3IdxMode(unsigned AM3Opc)
Definition ARMAddressingModes.h:441
unsigned getAM2Offset(unsigned AM2Opc)
Definition ARMAddressingModes.h:406
unsigned getThumbImmNonShiftedVal(unsigned V)
getThumbImmNonShiftedVal - If V is a value that satisfies isThumbImmShiftedVal, return the non-shiftd...
Definition ARMAddressingModes.h:248
unsigned getSOImmValRotate(unsigned Imm)
getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount ...
Definition ARMAddressingModes.h:115
bool isThumbImmShiftedVal(unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit im...
Definition ARMAddressingModes.h:221
AMSubMode
Definition ARMAddressingModes.h:66
@ da
Definition ARMAddressingModes.h:70
@ ib
Definition ARMAddressingModes.h:69
@ bad_am_submode
Definition ARMAddressingModes.h:67
@ db
Definition ARMAddressingModes.h:71
@ ia
Definition ARMAddressingModes.h:68
const char * getAMSubModeStr(AMSubMode Mode)
Definition ARMAddressingModes.h:74
unsigned getVMOVModImmVal(unsigned ModImm)
Definition ARMAddressingModes.h:539
float getFPImmFloat(unsigned Imm)
Definition ARMAddressingModes.h:631
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Definition ARMAddressingModes.h:307
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
Definition ARMAddressingModes.h:400
int getT2SOImmValRotateVal(unsigned V)
getT2SOImmValRotateVal - Return the 12-bit encoded representation if the specified value is a rotated...
Definition ARMAddressingModes.h:290
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
Definition ARMAddressingModes.h:476
unsigned getSOImmValRot(unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount.
Definition ARMAddressingModes.h:109
ShiftOpc getSORegShOp(unsigned Op)
Definition ARMAddressingModes.h:102
AddrOpc getAM5Op(unsigned AM5Opc)
Definition ARMAddressingModes.h:481
unsigned createVMOVModImm(unsigned OpCmode, unsigned Val)
Definition ARMAddressingModes.h:533
int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
Definition ARMAddressingModes.h:720
AddrOpc
Definition ARMAddressingModes.h:37
@ sub
Definition ARMAddressingModes.h:38
@ add
Definition ARMAddressingModes.h:39
bool isNEONi16splat(unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
Definition ARMAddressingModes.h:593
bool isSOImmTwoPartValNeg(unsigned V)
isSOImmTwoPartValNeg - Return true if the specified value can be obtained by two SOImmVal,...
Definition ARMAddressingModes.h:198
unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
Definition ARMAddressingModes.h:185
unsigned getVMOVModImmOpCmode(unsigned ModImm)
Definition ARMAddressingModes.h:536
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
Definition ARMAddressingModes.h:497
bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
Definition ARMAddressingModes.h:166
unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, unsigned IdxMode=0)
getAM3Opc - This function encodes the addrmode3 opc field.
Definition ARMAddressingModes.h:432
AddrOpc getAM5FP16Op(unsigned AM5Opc)
Definition ARMAddressingModes.h:504
unsigned getAM4ModeImm(AMSubMode SubMode)
Definition ARMAddressingModes.h:462
unsigned getThumbImm16ValShift(unsigned Imm)
getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed by a left shift.
Definition ARMAddressingModes.h:229
bool isNEONi32splat(unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
Definition ARMAddressingModes.h:611
int getFP16Imm(const APInt &Imm)
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
Definition ARMAddressingModes.h:654
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
Definition ARMAddressingModes.h:98
ShiftOpc
Definition ARMAddressingModes.h:27
@ lsr
Definition ARMAddressingModes.h:31
@ asr
Definition ARMAddressingModes.h:29
@ no_shift
Definition ARMAddressingModes.h:28
@ lsl
Definition ARMAddressingModes.h:30
@ rrx
Definition ARMAddressingModes.h:33
@ uxtw
Definition ARMAddressingModes.h:34
@ ror
Definition ARMAddressingModes.h:32
unsigned getShiftOpcEncoding(ShiftOpc Op)
Definition ARMAddressingModes.h:56
unsigned getT2SOImmTwoPartSecond(unsigned Imm)
Definition ARMAddressingModes.h:372
int getT2SOImmValSplatVal(unsigned V)
getT2SOImmValSplat - Return the 12-bit encoded representation if the specified value can be obtained ...
Definition ARMAddressingModes.h:262
const char * getAddrOpcStr(AddrOpc Op)
Definition ARMAddressingModes.h:42
StringRef getShiftOpcStr(ShiftOpc Op)
Definition ARMAddressingModes.h:44
int getFP32FP16Imm(const APInt &Imm)
If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding for it.
Definition ARMAddressingModes.h:679
unsigned getSOImmValImm(unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value.
Definition ARMAddressingModes.h:106
unsigned getT2SOImmTwoPartFirst(unsigned Imm)
Definition ARMAddressingModes.h:355
unsigned encodeNEONi32splat(unsigned Value)
Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
Definition ARMAddressingModes.h:617
bool isT2SOImmTwoPartVal(unsigned Imm)
Definition ARMAddressingModes.h:328
bool isNEONBytesplat(unsigned Value, unsigned Size)
Definition ARMAddressingModes.h:582
unsigned char getAM5Offset(unsigned AM5Opc)
Definition ARMAddressingModes.h:480
unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
Definition ARMAddressingModes.h:179
AddrOpc getAM2Op(unsigned AM2Opc)
Definition ARMAddressingModes.h:409
AddrOpc getAM3Op(unsigned AM3Opc)
Definition ARMAddressingModes.h:438
AMSubMode getAM4SubMode(unsigned Mode)
Definition ARMAddressingModes.h:458
unsigned getThumbImmValShift(unsigned Imm)
getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed by a left shift.
Definition ARMAddressingModes.h:210
bool isThumbImm16ShiftedVal(unsigned V)
isThumbImm16ShiftedVal - Return true if the specified value can be obtained by left shifting a 16-bit...
Definition ARMAddressingModes.h:240
This is an optimization pass for GlobalISel generic memory operations.
constexpr T rotr(T V, int R)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
To bit_cast(const From &from) noexcept
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
DWARFExpression::Operation Op
constexpr T rotl(T V, int R)