LLVM: llvm::ARM_AM Namespace Reference (original) (raw)

ARM_AM - ARM Addressing Mode Stuff. More...

Enumerations
enum ShiftOpc { no_shift = 0 , asr, lsl, lsr, ror, rrx, uxtw }
enum AddrOpc { sub = 0 , add }
enum AMSubMode { bad_am_submode = 0 , ia, ib, da, db }
Functions
static ShiftOpc getShiftOpcForNode (unsigned Opcode)
const char * getAddrOpcStr (AddrOpc Op)
StringRef getShiftOpcStr (ShiftOpc Op)
unsigned getShiftOpcEncoding (ShiftOpc Op)
const char * getAMSubModeStr (AMSubMode Mode)
unsigned getSORegOpc (ShiftOpc ShOp, unsigned Imm)
unsigned getSORegOffset (unsigned Op)
ShiftOpc getSORegShOp (unsigned Op)
unsigned getSOImmValImm (unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value.
unsigned getSOImmValRot (unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount.
unsigned getSOImmValRotate (unsigned Imm)
getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount to use.
int getSOImmVal (unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immediate operand, return the 12-bit encoding for it.
bool isSOImmTwoPartVal (unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVal's.
unsigned getSOImmTwoPartFirst (unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it.
unsigned getSOImmTwoPartSecond (unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of it.
bool isSOImmTwoPartValNeg (unsigned V)
isSOImmTwoPartValNeg - Return true if the specified value can be obtained by two SOImmVal, that -V = First + Second.
unsigned getThumbImmValShift (unsigned Imm)
getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed by a left shift.
bool isThumbImmShiftedVal (unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit immediate.
unsigned getThumbImm16ValShift (unsigned Imm)
getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed by a left shift.
bool isThumbImm16ShiftedVal (unsigned V)
isThumbImm16ShiftedVal - Return true if the specified value can be obtained by left shifting a 16-bit immediate.
unsigned getThumbImmNonShiftedVal (unsigned V)
getThumbImmNonShiftedVal - If V is a value that satisfies isThumbImmShiftedVal, return the non-shiftd value.
int getT2SOImmValSplatVal (unsigned V)
getT2SOImmValSplat - Return the 12-bit encoded representation if the specified value can be obtained by splatting the low 8 bits into every other byte or every byte of a 32-bit value.
int getT2SOImmValRotateVal (unsigned V)
getT2SOImmValRotateVal - Return the 12-bit encoded representation if the specified value is a rotated 8-bit value.
int getT2SOImmVal (unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_operand immediate operand, return the 12-bit encoding for it.
unsigned getT2SOImmValRotate (unsigned V)
bool isT2SOImmTwoPartVal (unsigned Imm)
unsigned getT2SOImmTwoPartFirst (unsigned Imm)
unsigned getT2SOImmTwoPartSecond (unsigned Imm)
unsigned getAM2Opc (AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getAM2Offset (unsigned AM2Opc)
AddrOpc getAM2Op (unsigned AM2Opc)
ShiftOpc getAM2ShiftOpc (unsigned AM2Opc)
unsigned getAM2IdxMode (unsigned AM2Opc)
unsigned getAM3Opc (AddrOpc Opc, unsigned char Offset, unsigned IdxMode=0)
getAM3Opc - This function encodes the addrmode3 opc field.
unsigned char getAM3Offset (unsigned AM3Opc)
AddrOpc getAM3Op (unsigned AM3Opc)
unsigned getAM3IdxMode (unsigned AM3Opc)
AMSubMode getAM4SubMode (unsigned Mode)
unsigned getAM4ModeImm (AMSubMode SubMode)
unsigned getAM5Opc (AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned char getAM5Offset (unsigned AM5Opc)
AddrOpc getAM5Op (unsigned AM5Opc)
unsigned getAM5FP16Opc (AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
unsigned char getAM5FP16Offset (unsigned AM5Opc)
AddrOpc getAM5FP16Op (unsigned AM5Opc)
unsigned createVMOVModImm (unsigned OpCmode, unsigned Val)
unsigned getVMOVModImmOpCmode (unsigned ModImm)
unsigned getVMOVModImmVal (unsigned ModImm)
uint64_t decodeVMOVModImm (unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element size in bits.
bool isNEONBytesplat (unsigned Value, unsigned Size)
bool isNEONi16splat (unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
unsigned encodeNEONi16splat (unsigned Value)
bool isNEONi32splat (unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
unsigned encodeNEONi32splat (unsigned Value)
Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
float getFPImmFloat (unsigned Imm)
int getFP16Imm (const APInt &Imm)
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
int getFP16Imm (const APFloat &FPImm)
int getFP32FP16Imm (const APInt &Imm)
If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding for it.
int getFP32FP16Imm (const APFloat &FPImm)
int getFP32Imm (const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
int getFP32Imm (const APFloat &FPImm)
int getFP64Imm (const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
int getFP64Imm (const APFloat &FPImm)

ARM_AM - ARM Addressing Mode Stuff.

◆ AddrOpc

◆ AMSubMode

◆ ShiftOpc

◆ createVMOVModImm()

◆ decodeVMOVModImm()

◆ encodeNEONi16splat()

◆ encodeNEONi32splat()

◆ getAddrOpcStr()

const char * llvm::ARM_AM::getAddrOpcStr ( AddrOpc Op) inline

◆ getAM2IdxMode()

◆ getAM2Offset()

◆ getAM2Op()

AddrOpc llvm::ARM_AM::getAM2Op ( unsigned AM2Opc) inline

◆ getAM2Opc()

◆ getAM2ShiftOpc()

ShiftOpc llvm::ARM_AM::getAM2ShiftOpc ( unsigned AM2Opc) inline

◆ getAM3IdxMode()

◆ getAM3Offset()

◆ getAM3Op()

AddrOpc llvm::ARM_AM::getAM3Op ( unsigned AM3Opc) inline

◆ getAM3Opc()

◆ getAM4ModeImm()

unsigned llvm::ARM_AM::getAM4ModeImm ( AMSubMode SubMode) inline

◆ getAM4SubMode()

AMSubMode llvm::ARM_AM::getAM4SubMode ( unsigned Mode) inline

◆ getAM5FP16Offset()

◆ getAM5FP16Op()

AddrOpc llvm::ARM_AM::getAM5FP16Op ( unsigned AM5Opc) inline

◆ getAM5FP16Opc()

◆ getAM5Offset()

◆ getAM5Op()

AddrOpc llvm::ARM_AM::getAM5Op ( unsigned AM5Opc) inline

◆ getAM5Opc()

◆ getAMSubModeStr()

const char * llvm::ARM_AM::getAMSubModeStr ( AMSubMode Mode) inline

◆ getFP16Imm() [1/2]

int llvm::ARM_AM::getFP16Imm ( const APFloat & FPImm) inline

◆ getFP16Imm() [2/2]

int llvm::ARM_AM::getFP16Imm ( const APInt & Imm) inline

◆ getFP32FP16Imm() [1/2]

int llvm::ARM_AM::getFP32FP16Imm ( const APFloat & FPImm) inline

◆ getFP32FP16Imm() [2/2]

int llvm::ARM_AM::getFP32FP16Imm ( const APInt & Imm) inline

◆ getFP32Imm() [1/2]

int llvm::ARM_AM::getFP32Imm ( const APFloat & FPImm) inline

◆ getFP32Imm() [2/2]

int llvm::ARM_AM::getFP32Imm ( const APInt & Imm) inline

◆ getFP64Imm() [1/2]

int llvm::ARM_AM::getFP64Imm ( const APFloat & FPImm) inline

◆ getFP64Imm() [2/2]

int llvm::ARM_AM::getFP64Imm ( const APInt & Imm) inline

◆ getFPImmFloat()

◆ getShiftOpcEncoding()

unsigned llvm::ARM_AM::getShiftOpcEncoding ( ShiftOpc Op) inline

◆ getShiftOpcForNode()

ShiftOpc llvm::ARM_AM::getShiftOpcForNode ( unsigned Opcode) inlinestatic

◆ getShiftOpcStr()

StringRef llvm::ARM_AM::getShiftOpcStr ( ShiftOpc Op) inline

◆ getSOImmTwoPartFirst()

◆ getSOImmTwoPartSecond()

◆ getSOImmVal()

int llvm::ARM_AM::getSOImmVal ( unsigned Arg) inline

getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immediate operand, return the 12-bit encoding for it.

If not, return -1.

Definition at line 149 of file ARMAddressingModes.h.

References getSOImmValRotate(), llvm::rotl(), and llvm::rotr().

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), llvm::ConstantMaterializationCost(), llvm::emitARMRegPlusImmediate(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::isLegalAddImmediate(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(), IsSingleInstrConstant(), llvm::LowerARMMachineInstrToMCInst(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMInstPrinter::printModImmOperand(), and llvm::rewriteARMFrameIndex().

◆ getSOImmValImm()

getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value.

Definition at line 106 of file ARMAddressingModes.h.

◆ getSOImmValRot()

getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount.

Definition at line 109 of file ARMAddressingModes.h.

◆ getSOImmValRotate()

◆ getSORegOffset()

◆ getSORegOpc()

◆ getSORegShOp()

ShiftOpc llvm::ARM_AM::getSORegShOp ( unsigned Op) inline

◆ getT2SOImmTwoPartFirst()

◆ getT2SOImmTwoPartSecond()

◆ getT2SOImmVal()

int llvm::ARM_AM::getT2SOImmVal ( unsigned Arg) inline

getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_operand immediate operand, return the 12-bit encoding for it.

If not, return -1. See ARM Reference Manual A6.3.2.

Definition at line 307 of file ARMAddressingModes.h.

References getT2SOImmValRotateVal(), getT2SOImmValSplatVal(), and llvm::Splat.

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), llvm::ConstantMaterializationCost(), llvm::emitT2RegPlusImmediate(), llvm::ARMTTIImpl::getIntImmCost(), getT2SOImmTwoPartFirst(), getT2SOImmTwoPartSecond(), llvm::ARMTargetLowering::isLegalAddImmediate(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(), isT2SOImmTwoPartVal(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), and llvm::rewriteT2FrameIndex().

◆ getT2SOImmValRotate()

◆ getT2SOImmValRotateVal()

int llvm::ARM_AM::getT2SOImmValRotateVal ( unsigned V) inline

◆ getT2SOImmValSplatVal()

int llvm::ARM_AM::getT2SOImmValSplatVal ( unsigned V) inline

getT2SOImmValSplat - Return the 12-bit encoded representation if the specified value can be obtained by splatting the low 8 bits into every other byte or every byte of a 32-bit value.

i.e., 00000000 00000000 00000000 abcdefgh control = 0 00000000 abcdefgh 00000000 abcdefgh control = 1 abcdefgh 00000000 abcdefgh 00000000 control = 2 abcdefgh abcdefgh abcdefgh abcdefgh control = 3 Return -1 if none of the above apply. See ARM Reference Manual A6.3.2.

Definition at line 262 of file ARMAddressingModes.h.

Referenced by getT2SOImmTwoPartFirst(), getT2SOImmVal(), and isT2SOImmTwoPartVal().

◆ getThumbImm16ValShift()

◆ getThumbImmNonShiftedVal()

◆ getThumbImmValShift()

◆ getVMOVModImmOpCmode()

◆ getVMOVModImmVal()

◆ isNEONBytesplat()

◆ isNEONi16splat()

◆ isNEONi32splat()

◆ isSOImmTwoPartVal()

◆ isSOImmTwoPartValNeg()

bool llvm::ARM_AM::isSOImmTwoPartValNeg ( unsigned V) inline

◆ isT2SOImmTwoPartVal()

bool llvm::ARM_AM::isT2SOImmTwoPartVal ( unsigned Imm) inline

◆ isThumbImm16ShiftedVal()

bool llvm::ARM_AM::isThumbImm16ShiftedVal ( unsigned V) inline

◆ isThumbImmShiftedVal()

bool llvm::ARM_AM::isThumbImmShiftedVal ( unsigned V) inline