ARMRegisterBankInfo.cpp Source File (original) (raw)

21#define GET_TARGET_REGBANK_IMPL

22#include "ARMGenRegisterBank.inc"

24using namespace llvm;

29namespace llvm {

30namespace ARM {

40 {0, 32, GPRRegBank},

42 {0, 32, FPRRegBank},

44 {0, 64, FPRRegBank},

45};

47#ifndef NDEBUG

49 unsigned Start, unsigned Length,

50 unsigned RegBankID) {

53}

58 "Wrong mapping for GPR");

61 "Wrong mapping for SPR");

64 "Wrong mapping for DPR");

65}

66#endif

77 {nullptr, 0},

91#ifndef NDEBUG

92static bool

101 "Wrong value mapping for 3 GPR ops instruction");

104 "Wrong value mapping for 3 GPR ops instruction");

107 "Wrong value mapping for 3 GPR ops instruction");

108

111 "Wrong value mapping for 3 SPR ops instruction");

114 "Wrong value mapping for 3 SPR ops instruction");

117 "Wrong value mapping for 3 SPR ops instruction");

118

121 "Wrong value mapping for 3 DPR ops instruction");

124 "Wrong value mapping for 3 DPR ops instruction");

127 "Wrong value mapping for 3 DPR ops instruction");

128}

129#endif

130}

131}

132

134

135

136

137

138

140

141 static auto InitializeRegisterBankOnce = [&]() {

143 (void)RBGPR;

144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");

145

146

147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&

148 "Subclass not added?");

149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&

150 "Subclass not added?");

151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&

152 "Subclass not added?");

153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&

154 "Subclass not added?");

155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&

156 "Subclass not added?");

157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&

158 "Subclass not added?");

159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&

160 "Subclass not added?");

162 "GPRs should hold up to 32-bit");

163

164#ifndef NDEBUG

167#endif

168 };

169

170 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);

171}

172

175 auto Opc = MI.getOpcode();

176

177

178

182 return Mapping;

183 }

184

186

189 unsigned NumOperands = MI.getNumOperands();

191

192 switch (Opc) {

193 case G_ADD:

194 case G_SUB: {

195

196

197 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

198 OperandsMapping = Ty.getSizeInBits() == 64

201 break;

202 }

203 case G_MUL:

204 case G_AND:

205 case G_OR:

206 case G_XOR:

207 case G_LSHR:

208 case G_ASHR:

209 case G_SHL:

210 case G_SDIV:

211 case G_UDIV:

212 case G_SEXT:

213 case G_ZEXT:

214 case G_ANYEXT:

215 case G_PTR_ADD:

216 case G_INTTOPTR:

217 case G_PTRTOINT:

218 case G_CTLZ:

219

220

222 break;

223 case G_TRUNC: {

224

225

226

227

228

229

230

231

232 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());

233 OperandsMapping =

238 break;

239 }

240 case G_LOAD:

241 case G_STORE: {

242 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

243 OperandsMapping =

244 Ty.getSizeInBits() == 64

248 break;

249 }

250 case G_FADD:

251 case G_FSUB:

252 case G_FMUL:

253 case G_FDIV:

254 case G_FNEG: {

255 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

256 OperandsMapping =Ty.getSizeInBits() == 64

259 break;

260 }

261 case G_FMA: {

262 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

263 OperandsMapping =

264 Ty.getSizeInBits() == 64

273 break;

274 }

275 case G_FPEXT: {

276 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());

277 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());

279 OperandsMapping =

282 break;

283 }

284 case G_FPTRUNC: {

285 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());

286 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());

288 OperandsMapping =

291 break;

292 }

293 case G_FPTOSI:

294 case G_FPTOUI: {

295 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());

296 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());

299 OperandsMapping =

305 break;

306 }

307 case G_SITOFP:

308 case G_UITOFP: {

309 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());

310 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());

313 OperandsMapping =

319 break;

320 }

321 case G_FCONSTANT: {

322 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

326 nullptr});

327 break;

328 }

329 case G_CONSTANT:

330 case G_FRAME_INDEX:

331 case G_GLOBAL_VALUE:

332 case G_CONSTANT_POOL:

333 OperandsMapping =

335 break;

336 case G_SELECT: {

337 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

338 (void)Ty;

339 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());

340 (void)Ty2;

341 assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");

343 OperandsMapping =

348 break;

349 }

350 case G_ICMP: {

351 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());

352 (void)Ty2;

354 OperandsMapping =

358 break;

359 }

360 case G_FCMP: {

361 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

362 (void)Ty;

363 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());

364 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());

365 (void)Ty2;

366 assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");

368 "Mismatched operand sizes for G_FCMP");

369

371 assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");

372

375 OperandsMapping =

377 FPRValueMapping, FPRValueMapping});

378 break;

379 }

380 case G_MERGE_VALUES: {

381

382

383 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

384 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());

385 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());

386 if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||

389 OperandsMapping =

393 break;

394 }

395 case G_UNMERGE_VALUES: {

396

397

398 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

399 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());

400 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());

401 if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||

404 OperandsMapping =

408 break;

409 }

410 case G_BR:

412 break;

413 case G_BRCOND:

414 OperandsMapping =

416 break;

417 case DBG_VALUE: {

420 if (MaybeReg.isReg() && MaybeReg.getReg()) {

421 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();

426 }

428 break;

429 }

430 case G_GET_FPENV:

431 case G_SET_FPENV:

432 case G_GET_FPMODE:

433 OperandsMapping =

435 break;

436 case G_RESET_FPENV:

438 break;

439 default:

441 }

442

443#ifndef NDEBUG

444 for (unsigned i = 0; i < NumOperands; i++) {

445 for (const auto &Mapping : OperandsMapping[i]) {

447 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||

449 "Trying to use floating point register bank on target without vfp");

450 }

451 }

452#endif

453

455 NumOperands);

456}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file declares the targeting of the RegisterBankInfo class for ARM.

ARMRegisterBankInfo(const TargetRegisterInfo &TRI)

Definition ARMRegisterBankInfo.cpp:133

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

Get the mapping of the different operands of MI on the register bank.

Definition ARMRegisterBankInfo.cpp:174

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

bool isValid() const

Check whether this object is valid.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

unsigned getMaximumSize(unsigned RegBankID) const

Get the maximum size in bits that fits in the given register bank.

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

This class implements the register bank concept.

LLVM_ABI bool covers(const TargetRegisterClass &RC) const

Check whether this register bank covers RC.

unsigned getID() const

Get the identifier of this register bank.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Define some predicates that are used for node matching.

const RegisterBankInfo::PartialMapping PartMappings[]

Definition ARMRegisterBankInfo.cpp:38

static void checkPartialMappings()

Definition ARMRegisterBankInfo.cpp:55

ValueMappingIdx

Definition ARMRegisterBankInfo.cpp:68

@ SPR3OpsIdx

Definition ARMRegisterBankInfo.cpp:71

@ InvalidIdx

Definition ARMRegisterBankInfo.cpp:69

@ GPR3OpsIdx

Definition ARMRegisterBankInfo.cpp:70

@ DPR3OpsIdx

Definition ARMRegisterBankInfo.cpp:72

static void checkValueMappings()

Definition ARMRegisterBankInfo.cpp:98

const RegisterBankInfo::ValueMapping ValueMappings[]

Definition ARMRegisterBankInfo.cpp:75

static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, const RegisterBankInfo::PartialMapping *BreakDown)

Definition ARMRegisterBankInfo.cpp:93

PartialMappingIdx

Definition ARMRegisterBankInfo.cpp:31

@ PMI_DPR

Definition ARMRegisterBankInfo.cpp:34

@ PMI_GPR

Definition ARMRegisterBankInfo.cpp:32

@ PMI_Min

Definition ARMRegisterBankInfo.cpp:35

@ PMI_SPR

Definition ARMRegisterBankInfo.cpp:33

static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)

Definition ARMRegisterBankInfo.cpp:48

Invariant opcodes: All instruction sets have these as their low opcodes.

This is an optimization pass for GlobalISel generic memory operations.

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

void call_once(once_flag &flag, Function &&F, Args &&... ArgList)

Execute the function specified as a parameter once.

Helper struct that represents how a value is partially mapped into a register.

unsigned StartIdx

Number of bits at which this partial mapping starts in the original value.

const RegisterBank * RegBank

unsigned Length

Length of this mapping in bits.

Helper struct that represents how a value is mapped through different register banks.

unsigned NumBreakDowns

Number of partial mapping to break down this value.

const PartialMapping * BreakDown

How the value is broken down between the different register banks.

The llvm::once_flag structure.