LLVM: llvm::ARM Namespace Reference (original) (raw)

Define some predicates that are used for node matching. More...

Classes
struct	ArchNames
struct	CpuNames
struct	ExtName
struct	FPUName
struct	ParsedBranchProtection

Enumerations
enum	ARMABI { ARM_ABI_UNKNOWN, ARM_ABI_APCS, ARM_ABI_AAPCS, ARM_ABI_AAPCS16 }
enum	ArchExtKind : uint64_t { AEK_INVALID = 0 , AEK_NONE = 1 , AEK_CRC = 1 << 1 , AEK_CRYPTO = 1 << 2 , AEK_FP = 1 << 3 , AEK_HWDIVTHUMB = 1 << 4 , AEK_HWDIVARM = 1 << 5 , AEK_MP = 1 << 6 , AEK_SIMD = 1 << 7 , AEK_SEC = 1 << 8 , AEK_VIRT = 1 << 9 , AEK_DSP = 1 << 10 , AEK_FP16 = 1 << 11 , AEK_RAS = 1 << 12 , AEK_DOTPROD = 1 << 13 , AEK_SHA2 = 1 << 14 , AEK_AES = 1 << 15 , AEK_FP16FML = 1 << 16 , AEK_SB = 1 << 17 , AEK_FP_DP = 1 << 18 , AEK_LOB = 1 << 19 , AEK_BF16 = 1 << 20 , AEK_I8MM = 1 << 21 , AEK_CDECP0 = 1 << 22 , AEK_CDECP1 = 1 << 23 , AEK_CDECP2 = 1 << 24 , AEK_CDECP3 = 1 << 25 , AEK_CDECP4 = 1 << 26 , AEK_CDECP5 = 1 << 27 , AEK_CDECP6 = 1 << 28 , AEK_CDECP7 = 1 << 29 , AEK_PACBTI = 1 << 30 , AEK_MVE = 1ULL << 31 , AEK_OS = 1ULL << 59 , AEK_IWMMXT = 1ULL << 60 , AEK_IWMMXT2 = 1ULL << 61 , AEK_MAVERICK = 1ULL << 62 , AEK_XSCALE = 1ULL << 63 }
enum class	ArchKind { ARM_FPU }
enum	FPUKind { ARM_FPU, ARM_FPU }
enum class	FPUVersion { NONE, VFPV2, VFPV3, VFPV3_FP16, VFPV4, VFPV5, VFPV5_FULLFP16 }
enum class	FPURestriction { None = 0 , D16, SP_D16 }
enum class	NeonSupportLevel { None = 0 , Neon, Crypto }
enum class	ProfileKind { INVALID = 0 , A, R, M }
enum class	ISAKind { INVALID = 0 , ARM, THUMB, AARCH64 }
enum class	EndianKind { INVALID = 0 , LITTLE, BIG }
enum	DW_ISA { DW_ISA_ARM_thumb = 1 , DW_ISA_ARM_arm = 2 }
enum	Rounding { RN = 0 , RP = 1 , RM = 2 , RZ = 3 , rmMask = 3 }
	Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR. More...
enum	PartialMappingIdx { PMI_GPR, PMI_SPR, PMI_DPR, PMI_Min = PMI_GPR }
enum	ValueMappingIdx { InvalidIdx = 0 , GPR3OpsIdx = 1 , SPR3OpsIdx = 4 , DPR3OpsIdx = 7 }
enum	Fixups { fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind , fixup_t2_ldst_pcrel_12, fixup_arm_pcrel_10_unscaled, fixup_arm_pcrel_10, fixup_t2_pcrel_10, fixup_arm_pcrel_9, fixup_t2_pcrel_9, fixup_arm_ldst_abs_12, fixup_thumb_adr_pcrel_10, fixup_arm_adr_pcrel_12, fixup_t2_adr_pcrel_12, fixup_arm_condbranch, fixup_arm_uncondbranch, fixup_t2_condbranch, fixup_t2_uncondbranch, fixup_arm_thumb_br, fixup_arm_uncondbl, fixup_arm_condbl, fixup_arm_blx, fixup_arm_thumb_bl, fixup_arm_thumb_blx, fixup_arm_thumb_cb, fixup_arm_thumb_cp, fixup_arm_thumb_bcc, fixup_arm_movt_hi16, fixup_arm_movw_lo16, fixup_t2_movt_hi16, fixup_t2_movw_lo16, fixup_arm_thumb_upper_8_15, fixup_arm_thumb_upper_0_7, fixup_arm_thumb_lower_8_15, fixup_arm_thumb_lower_0_7, fixup_arm_mod_imm, fixup_t2_so_imm, fixup_bf_branch, fixup_bf_target, fixup_bfl_target, fixup_bfc_target, fixup_bfcsel_else_target, fixup_wls, fixup_le, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	{ S_None, S_COFF_SECREL, S_HI16, S_LO16, S_HI_8_15, S_HI_0_7, S_LO_8_15, S_LO_0_7, S_ARM_NONE, S_FUNCDESC, S_GOT, S_GOTFUNCDESC, S_GOTOFF, S_GOTOFFFUNCDESC, S_GOTTPOFF, S_GOTTPOFF_FDPIC, S_GOT_PREL, S_PLT, S_PREL31, S_SBREL, S_TARGET1, S_TARGET2, S_TLSCALL, S_TLSDESC, S_TLSDESCSEQ, S_TLSGD, S_TLSGD_FDPIC, S_TLSLDM, S_TLSLDM_FDPIC, S_TLSLDO, S_TPOFF }
enum	OperandType { OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET , OPERAND_VPRED_N }
enum class	PredBlockMask { T = 0b1000 , TT = 0b0100 , TE = 0b1100 , TTT = 0b0010 , TTE = 0b0110 , TEE = 0b1110 , TET = 0b1010 , TTTT = 0b0001 , TTTE = 0b0011 , TTEE = 0b0111 , TTET = 0b0101 , TEEE = 0b1111 , TEET = 0b1101 , TETT = 0b1001 , TETE = 0b1011 }
	Mask values for IT and VPT Blocks, to be used by MCOperands. More...

Functions
bool	isDoublePrecision (const FPURestriction restriction)
bool	has32Regs (const FPURestriction restriction)
ArchKind &	operator-- (ArchKind &Kind)
LLVM_ABI StringRef	getFPUName (FPUKind FPUKind)
LLVM_ABI FPUVersion	getFPUVersion (FPUKind FPUKind)
LLVM_ABI NeonSupportLevel	getFPUNeonSupportLevel (FPUKind FPUKind)
LLVM_ABI FPURestriction	getFPURestriction (FPUKind FPUKind)
LLVM_ABI bool	getFPUFeatures (FPUKind FPUKind, std::vector< StringRef > &Features)
LLVM_ABI bool	getHWDivFeatures (uint64_t HWDivKind, std::vector< StringRef > &Features)
LLVM_ABI bool	getExtensionFeatures (uint64_t Extensions, std::vector< StringRef > &Features)
LLVM_ABI StringRef	getArchName (ArchKind AK)
LLVM_ABI unsigned	getArchAttr (ArchKind AK)
LLVM_ABI StringRef	getCPUAttr (ArchKind AK)
LLVM_ABI StringRef	getSubArch (ArchKind AK)
LLVM_ABI StringRef	getArchExtName (uint64_t ArchExtKind)
LLVM_ABI StringRef	getArchExtFeature (StringRef ArchExt)
LLVM_ABI bool	appendArchExtFeatures (StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)
LLVM_ABI ArchKind	convertV9toV8 (ArchKind AK)
LLVM_ABI FPUKind	getDefaultFPU (StringRef CPU, ArchKind AK)
LLVM_ABI uint64_t	getDefaultExtensions (StringRef CPU, ArchKind AK)
LLVM_ABI StringRef	getDefaultCPU (StringRef Arch)
LLVM_ABI StringRef	getFPUSynonym (StringRef FPU)
LLVM_ABI uint64_t	parseHWDiv (StringRef HWDiv)
LLVM_ABI FPUKind	parseFPU (StringRef FPU)
LLVM_ABI ArchKind	parseArch (StringRef Arch)
LLVM_ABI uint64_t	parseArchExt (StringRef ArchExt)
LLVM_ABI ArchKind	parseCPUArch (StringRef CPU)
LLVM_ABI ProfileKind	parseArchProfile (StringRef Arch)
LLVM_ABI unsigned	parseArchVersion (StringRef Arch)
LLVM_ABI void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values)
LLVM_ABI LLVM_READONLY StringRef	computeDefaultTargetABI (const Triple &TT)
LLVM_ABI LLVM_READONLY ARMABI	computeTargetABI (const Triple &TT, StringRef ABIName="")
LLVM_ABI StringRef	getARMCPUForArch (const llvm::Triple &Triple, StringRef MArch={})
	Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
LLVM_ABI void	PrintSupportedExtensions (StringMap< StringRef > DescMap)
LLVM_ABI StringRef	getArchSynonym (StringRef Arch)
	Converts e.g. "armv8" -> "armv8-a".
LLVM_ABI StringRef	getCanonicalArchName (StringRef Arch)
	MArch is expected to be of the form (arm\|thumb)?(eb)?(v.
LLVM_ABI ISAKind	parseArchISA (StringRef Arch)
LLVM_ABI EndianKind	parseArchEndian (StringRef Arch)
LLVM_ABI bool	parseBranchProtection (StringRef Spec, ParsedBranchProtection &PBP, StringRef &Err, bool EnablePAuthLR=false)
bool	isBitFieldInvertedMask (unsigned v)
FastISel *	createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
static bool	checkPartMapping (const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)
static void	checkPartialMappings ()
static bool	checkValueMapping (const RegisterBankInfo::ValueMapping &VM, const RegisterBankInfo::PartialMapping *BreakDown)
static void	checkValueMappings ()
void	printSpecifierExpr (const MCAsmInfo &MAI, raw_ostream &OS, const MCSpecifierExpr &Expr)
const MCSpecifierExpr *	createUpper16 (const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr *	createLower16 (const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr *	createUpper8_15 (const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr *	createUpper0_7 (const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr *	createLower8_15 (const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr *	createLower0_7 (const MCExpr *Expr, MCContext &Ctx)
bool	isVpred (OperandType op)
bool	isVpred (uint8_t op)
bool	isCDECoproc (size_t Coproc, const MCSubtargetInfo &STI)

Variables
constexpr ExtName	ARCHExtNames []
struct {
StringRef llvm::ARM::Name
uint64_t llvm::ARM::ID
}	HWDivNames []
constexpr CpuNames	CPUNames []
static constexpr FPUName	FPUNames []
static constexpr ArchNames	ARMArchNames []
const unsigned	RoundingBitsPos = 22
const unsigned	FPStatusBits = 0xf800009f
const unsigned	FPReservedBits = 0x00006060
const RegisterBankInfo::PartialMapping	PartMappings []
const RegisterBankInfo::ValueMapping	ValueMappings []

Define some predicates that are used for node matching.

◆ Specifier

◆ anonymous enum

Enumerator
S_None
S_COFF_SECREL
S_HI16
S_LO16
S_HI_8_15
S_HI_0_7
S_LO_8_15
S_LO_0_7
S_ARM_NONE
S_FUNCDESC
S_GOT
S_GOTFUNCDESC
S_GOTOFF
S_GOTOFFFUNCDESC
S_GOTTPOFF
S_GOTTPOFF_FDPIC
S_GOT_PREL
S_PLT
S_PREL31
S_SBREL
S_TARGET1
S_TARGET2
S_TLSCALL
S_TLSDESC
S_TLSDESCSEQ
S_TLSGD
S_TLSGD_FDPIC
S_TLSLDM
S_TLSLDM_FDPIC
S_TLSLDO
S_TPOFF

Definition at line 93 of file ARMMCAsmInfo.h.

◆ ArchExtKind

Enumerator
AEK_INVALID
AEK_NONE
AEK_CRC
AEK_CRYPTO
AEK_FP
AEK_HWDIVTHUMB
AEK_HWDIVARM
AEK_MP
AEK_SIMD
AEK_SEC
AEK_VIRT
AEK_DSP
AEK_FP16
AEK_RAS
AEK_DOTPROD
AEK_SHA2
AEK_AES
AEK_FP16FML
AEK_SB
AEK_FP_DP
AEK_LOB
AEK_BF16
AEK_I8MM
AEK_CDECP0
AEK_CDECP1
AEK_CDECP2
AEK_CDECP3
AEK_CDECP4
AEK_CDECP5
AEK_CDECP6
AEK_CDECP7
AEK_PACBTI
AEK_MVE
AEK_OS
AEK_IWMMXT
AEK_IWMMXT2
AEK_MAVERICK
AEK_XSCALE

Definition at line 39 of file ARMTargetParser.h.

◆ ArchKind

enum class llvm::ARM::ArchKind	strong

◆ ARMABI

Enumerator
ARM_ABI_UNKNOWN
ARM_ABI_APCS
ARM_ABI_AAPCS
ARM_ABI_AAPCS16

Definition at line 30 of file ARMTargetParser.h.

◆ DW_ISA

Enumerator
DW_ISA_ARM_thumb
DW_ISA_ARM_arm

Definition at line 25 of file ARMAsmPrinter.h.

◆ EndianKind

enum class llvm::ARM::EndianKind	strong

◆ Fixups

Enumerator
fixup_arm_ldst_pcrel_12
fixup_t2_ldst_pcrel_12
fixup_arm_pcrel_10_unscaled
fixup_arm_pcrel_10
fixup_t2_pcrel_10
fixup_arm_pcrel_9
fixup_t2_pcrel_9
fixup_arm_ldst_abs_12
fixup_thumb_adr_pcrel_10
fixup_arm_adr_pcrel_12
fixup_t2_adr_pcrel_12
fixup_arm_condbranch
fixup_arm_uncondbranch
fixup_t2_condbranch
fixup_t2_uncondbranch
fixup_arm_thumb_br
fixup_arm_uncondbl
fixup_arm_condbl
fixup_arm_blx
fixup_arm_thumb_bl
fixup_arm_thumb_blx
fixup_arm_thumb_cb
fixup_arm_thumb_cp
fixup_arm_thumb_bcc
fixup_arm_movt_hi16
fixup_arm_movw_lo16
fixup_t2_movt_hi16
fixup_t2_movw_lo16
fixup_arm_thumb_upper_8_15
fixup_arm_thumb_upper_0_7
fixup_arm_thumb_lower_8_15
fixup_arm_thumb_lower_0_7
fixup_arm_mod_imm
fixup_t2_so_imm
fixup_bf_branch
fixup_bf_target
fixup_bfl_target
fixup_bfc_target
fixup_bfcsel_else_target
fixup_wls
fixup_le
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file ARMFixupKinds.h.

◆ FPUKind

◆ FPURestriction

Enumerator
None	No restriction.
D16	Only 16 D registers.
SP_D16	Only single-precision instructions, with 16 D registers.

Definition at line 149 of file ARMTargetParser.h.

◆ FPUVersion

enum class llvm::ARM::FPUVersion	strong

Enumerator
NONE
VFPV2
VFPV3
VFPV3_FP16
VFPV4
VFPV5
VFPV5_FULLFP16

Definition at line 138 of file ARMTargetParser.h.

◆ ISAKind

enum class llvm::ARM::ISAKind	strong

◆ NeonSupportLevel

Enumerator
None	No Neon.
Neon	Neon.
Crypto	Neon with Crypto.

Definition at line 164 of file ARMTargetParser.h.

◆ OperandType

◆ PartialMappingIdx

◆ PredBlockMask

Mask values for IT and VPT Blocks, to be used by MCOperands.

Note that this is different from the "real" encoding used by the instructions. In this encoding, the lowest set bit indicates the end of the encoding, and above that, "1" indicates an else, while "0" indicates a then. Tx = x100 Txy = xy10 Txyz = xyz1

Enumerator
T
TT
TE
TTT
TTE
TEE
TET
TTTT
TTTE
TTEE
TTET
TEEE
TEET
TETT
TETE

Definition at line 105 of file ARMBaseInfo.h.

◆ ProfileKind

enum class llvm::ARM::ProfileKind	strong

◆ Rounding

Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.

Enumerator
RN
RP
RM
RZ
rmMask

Definition at line 57 of file ARMISelLowering.h.

◆ ValueMappingIdx

◆ appendArchExtFeatures()

◆ checkPartialMappings()

void llvm::ARM::checkPartialMappings ( )	static

◆ checkPartMapping()

◆ checkValueMapping()

◆ checkValueMappings()

void llvm::ARM::checkValueMappings ( )	static

Definition at line 98 of file ARMRegisterBankInfo.cpp.

References assert(), checkValueMapping(), DPR3OpsIdx, GPR3OpsIdx, PartMappings, PMI_DPR, PMI_GPR, PMI_Min, PMI_SPR, SPR3OpsIdx, and ValueMappings.

Referenced by llvm::ARMRegisterBankInfo::ARMRegisterBankInfo().

◆ computeDefaultTargetABI()

Definition at line 540 of file ARMTargetParser.cpp.

References llvm::Triple::Android, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, llvm::Triple::GNUEABIHFT64, llvm::Triple::GNUEABIT64, M, llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, llvm::Triple::OpenHOS, parseArchProfile(), TT, and llvm::Triple::UnknownOS.

Referenced by computeTargetABI().

◆ computeTargetABI()

◆ convertV9toV8()

ARM::ArchKind llvm::ARM::convertV9toV8	(	ARM::ArchKind	AK	)

◆ createFastISel()

◆ createLower0_7()

◆ createLower16()

◆ createLower8_15()

◆ createUpper0_7()

◆ createUpper16()

◆ createUpper8_15()

◆ fillValidCPUArchList()

◆ getArchAttr()

◆ getArchExtFeature()

◆ getArchExtName()

◆ getArchName()

◆ getArchSynonym()

◆ getARMCPUForArch()

Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.

Parameters

Arch	the architecture name (e.g., "armv7s"). If it is an empty string then the triple's arch name is used.

Definition at line 595 of file ARMTargetParser.cpp.

References llvm::Triple::DriverKit, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::StringRef::empty(), llvm::Triple::FreeBSD, llvm::Triple::Fuchsia, llvm::Triple::getArchName(), getCanonicalArchName(), getDefaultCPU(), llvm::Triple::getEnvironment(), llvm::Triple::getOS(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, llvm::Triple::GNUEABIHFT64, llvm::Triple::Haiku, llvm::Triple::IOS, llvm_unreachable, llvm::Triple::MacOSX, llvm::Triple::MuslEABIHF, llvm::Triple::NetBSD, llvm::Triple::OpenBSD, parseArchVersion(), llvm::Triple::TvOS, llvm::Triple::WatchOS, llvm::Triple::Win32, and llvm::Triple::XROS.

◆ getCanonicalArchName()

MArch is expected to be of the form (arm|thumb)?(eb)?(v.

+)?(eb)?, but (iwmmxt|xscale)(eb)? is also permitted. If the former, return "v.+", if the latter, return unmodified string, minus 'eb'. If invalid, return empty string.

Definition at line 56 of file ARMTargetParserCommon.cpp.

References A, and llvm::StringRef::npos.

Referenced by getARMCPUForArch(), llvm::AArch64::parseArch(), parseArch(), parseArchProfile(), parseArchVersion(), parseARMArch(), and parseSubArch().