LLVM: lib/Target/ARM/ARMSubtarget.cpp Source File (original) (raw)
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41using namespace llvm;
42
43#define DEBUG_TYPE "arm-subtarget"
44
45#define GET_SUBTARGETINFO_TARGET_DESC
46#define GET_SUBTARGETINFO_CTOR
47#include "ARMGenSubtargetInfo.inc"
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52
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61 "Generate any type of IT block"),
63 "Disallow complex IT blocks")));
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75 initializeEnvironment();
76 initSubtargetFeatures(CPU, FS);
77 return *this;
78}
79
85
87}
88
90 const std::string &FS,
92 bool MinSize)
94 UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
95 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
96 FrameLowering(initializeFrameLowering(CPU, FS)),
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99 InstrInfo(isThumb1Only()
104 TLInfo(TM, *this) {
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116 RegBankInfo.reset(RBI);
117}
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120 return CallLoweringInfo.get();
121}
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124 return InstSelector.get();
125}
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129}
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132 return RegBankInfo.get();
133}
134
136
138}
139
140void ARMSubtarget::initializeEnvironment() {
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150 "inconsistent sjlj choice between CodeGen and MC");
151}
152
153void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
156
160 if (AK == ARM::ArchKind::ARMV7S)
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163 else if (AK == ARM::ArchKind::ARMV7K)
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167 }
168 }
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174 if (.empty()) {
175 if (!ArchFS.empty())
176 ArchFS = (Twine(ArchFS) + "," + FS).str();
177 else
178 ArchFS = std::string(FS);
179 }
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182
183
184 assert(hasV6T2Ops() || !hasThumb2());
185
186 if (genExecuteOnly()) {
187
188 if (hasV8MBaselineOps())
189 NoMovt = false;
190 if (!hasV6MOps())
191 report_fatal_error("Cannot generate execute-only code for this target");
192 }
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202 NoARM = true;
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232 switch (IT) {
235 break;
238 break;
239 }
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243 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) &&
245 HasNEONForFP = true;
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248 ReserveR9 = true;
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257 case CortexA5:
258 break;
259 case CortexA7:
261 break;
262 case CortexA8:
264 break;
265 case CortexA9:
268 break;
269 case CortexA12:
270 break;
271 case CortexA15:
275 break;
276 case CortexA17:
277 case CortexA32:
278 case CortexA35:
279 case CortexA53:
280 case CortexA55:
281 case CortexA57:
282 case CortexA72:
283 case CortexA73:
284 case CortexA75:
285 case CortexA76:
286 case CortexA77:
287 case CortexA78:
288 case CortexA78AE:
289 case CortexA78C:
290 case CortexA510:
291 case CortexA710:
292 case CortexR4:
293 case CortexR5:
294 case CortexR7:
295 case CortexM3:
296 case CortexM55:
297 case CortexM7:
298 case CortexM85:
299 case CortexR52:
300 case CortexR52plus:
301 case CortexX1:
302 case CortexX1C:
303 break;
304 case Exynos:
309 break;
310 case Kryo:
311 break;
312 case Krait:
314 break;
315 case NeoverseV1:
316 break;
322 break;
323 }
324}
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331}
336}
340}
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345}
349}
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353 return true;
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360 return true;
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362 return false;
363}
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367}
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371}
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380 return false;
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384}
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389 return hasMVEIntegerOps();
390}
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396}
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403 return false;
404 if (disablePostRAScheduler())
405 return false;
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408}
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412 return false;
413 if (disablePostRAScheduler())
414 return false;
416}
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424}
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430 return !NoMovt && hasV8MBaselineOps() &&
432}
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437 return true;
438
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440 if (!hasV6Ops())
441 return false;
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447}
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463 return 2;
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473 return 3;
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477 return 1;
478}
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481 unsigned PhysReg) const {
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488 ARM::GPRRegClass.contains(PhysReg);
489}
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495 const std::vector CSI =
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516 F.needsUnwindTableEntry() &&
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528}
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for ARM.
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isTargetHardFloat() const
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool shouldSignReturnAddress() const
This class provides the information for the target register banks.
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
const Triple & getTargetTriple() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
const ARMBaseTargetMachine & TM
bool isThumb1Only() const
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
bool useDFAforSMS() const override
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
MCPhysReg getFramePointerReg() const
bool isTargetWindows() const
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
const ARMTargetLowering * getTargetLowering() const override
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
std::string CPUString
CPUString - String name of used CPU.
unsigned getMispredictionPenalty() const
unsigned PreferBranchLogAlignment
What alignment is preferred for loop bodies and functions, in log2(bytes).
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isTargetDarwin() const
const ARMBaseRegisterInfo * getRegisterInfo() const override
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
InstructionSelector * getInstructionSelector() const override
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
enum PushPopSplitVariation getPushPopSplitVariation(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
PushPopSplitVariation
How the push and pop instructions of callee saved general-purpose registers should be split.
@ SplitR11WindowsSEH
When the stack frame size is not known (because of variable-sized objects or realignment),...
@ SplitR7
R7 and LR must be adjacent, because R7 is the frame pointer, and must point to a frame record consist...
@ SplitR11AAPCSSignRA
When generating AAPCS-compilant frame chains, R11 is the frame pointer, and must be pushed adjacent t...
@ NoSplit
All GPRs can be pushed in a single instruction.
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool isTargetNaCl() const
bool isTargetWatchABI() const
const TargetOptions & Options
Options passed via command line that could influence the target.
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
@ DoubleIssue
Can load/store 2 registers/cycle.
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useMachinePipeliner() const
bool useMachineScheduler() const
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
bool isTargetHardFloat() const
Container class for subtarget features.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
bool isDeclarationForLinker() const
bool hasCommonLinkage() const
bool usesWindowsCFI() const
ExceptionHandling getExceptionHandlingType() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
bool isPositionIndependent() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
bool FramePointerIsReserved(const MachineFunction &MF) const
FramePointerIsReserved - This returns true if the frame pointer must always either point to a new fra...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
ExceptionHandling ExceptionModel
What exception model to use.
Triple - Helper class for working with autoconf configuration names.
StringRef getArchName() const
Get the architecture (first) component of the triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
ArchKind parseArch(StringRef Arch)
@ Swift
Calling convention for Swift.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This struct is a compact representation of a valid (non-zero power of two) alignment.
unsigned MispredictPenalty