ARMSubtarget.cpp Source File (original) (raw)

41using namespace llvm;

43#define DEBUG_TYPE "arm-subtarget"

45#define GET_SUBTARGETINFO_TARGET_DESC

46#define GET_SUBTARGETINFO_CTOR

47#include "ARMGenSubtargetInfo.inc"

61 "Generate any type of IT block"),

63 "Disallow complex IT blocks")));

75 initSubtargetFeatures(CPU, FS);

76 return *this;

77}

86}

89 const std::string &FS,

95 FrameLowering(initializeFrameLowering(CPU, FS)),

101 TLInfo(TM, *this) {

102

105

107

108

109

110

112

113 RegBankInfo.reset(RBI);

114}

115

117 return CallLoweringInfo.get();

118}

119

121 return InstSelector.get();

122}

123

125 return Legalizer.get();

126}

127

129 return RegBankInfo.get();

130}

131

134 if (TT.isOSBinFormatMachO()) {

135

137

138 static const struct {

139 const RTLIB::Libcall Op;

140 const RTLIB::LibcallImpl Impl;

141 } LibraryCalls[] = {

142

143 { RTLIB::ADD_F32, RTLIB::impl___addsf3vfp },

144 { RTLIB::SUB_F32, RTLIB::impl___subsf3vfp },

145 { RTLIB::MUL_F32, RTLIB::impl___mulsf3vfp },

146 { RTLIB::DIV_F32, RTLIB::impl___divsf3vfp },

147

148

149 { RTLIB::ADD_F64, RTLIB::impl___adddf3vfp },

150 { RTLIB::SUB_F64, RTLIB::impl___subdf3vfp },

151 { RTLIB::MUL_F64, RTLIB::impl___muldf3vfp },

152 { RTLIB::DIV_F64, RTLIB::impl___divdf3vfp },

153

154

155 { RTLIB::OEQ_F32, RTLIB::impl___eqsf2vfp },

156 { RTLIB::UNE_F32, RTLIB::impl___nesf2vfp },

157 { RTLIB::OLT_F32, RTLIB::impl___ltsf2vfp },

158 { RTLIB::OLE_F32, RTLIB::impl___lesf2vfp },

159 { RTLIB::OGE_F32, RTLIB::impl___gesf2vfp },

160 { RTLIB::OGT_F32, RTLIB::impl___gtsf2vfp },

161 { RTLIB::UO_F32, RTLIB::impl___unordsf2vfp },

162

163

164 { RTLIB::OEQ_F64, RTLIB::impl___eqdf2vfp },

165 { RTLIB::UNE_F64, RTLIB::impl___nedf2vfp },

166 { RTLIB::OLT_F64, RTLIB::impl___ltdf2vfp },

167 { RTLIB::OLE_F64, RTLIB::impl___ledf2vfp },

168 { RTLIB::OGE_F64, RTLIB::impl___gedf2vfp },

169 { RTLIB::OGT_F64, RTLIB::impl___gtdf2vfp },

170 { RTLIB::UO_F64, RTLIB::impl___unorddf2vfp },

171

172

173

174

175 { RTLIB::FPTOSINT_F64_I32, RTLIB::impl___fixdfsivfp },

176 { RTLIB::FPTOUINT_F64_I32, RTLIB::impl___fixunsdfsivfp },

177 { RTLIB::FPTOSINT_F32_I32, RTLIB::impl___fixsfsivfp },

178 { RTLIB::FPTOUINT_F32_I32, RTLIB::impl___fixunssfsivfp },

179

180

181 { RTLIB::FPROUND_F64_F32, RTLIB::impl___truncdfsf2vfp },

182 { RTLIB::FPEXT_F32_F64, RTLIB::impl___extendsfdf2vfp },

183

184

185

186

187

188

189 { RTLIB::SINTTOFP_I32_F64, RTLIB::impl___floatsidfvfp },

190 { RTLIB::UINTTOFP_I32_F64, RTLIB::impl___floatunssidfvfp },

191 { RTLIB::SINTTOFP_I32_F32, RTLIB::impl___floatsisfvfp },

192 { RTLIB::UINTTOFP_I32_F32, RTLIB::impl___floatunssisfvfp },

193 };

194

195

196 for (const auto &LC : LibraryCalls)

197 Info.setLibcallImpl(LC.Op, LC.Impl);

198 }

199 }

200}

201

206

207void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {

210

214 if (AK == ARM::ArchKind::ARMV7S)

215

217 else if (AK == ARM::ArchKind::ARMV7K)

218

219

221 }

222 }

223

224

225

226

228 if (.empty()) {

229 if (!ArchFS.empty())

230 ArchFS = (Twine(ArchFS) + "," + FS).str();

231 else

232 ArchFS = std::string(FS);

233 }

235

236

237

238 assert(hasV6T2Ops() || !hasThumb2());

239

240 if (genExecuteOnly()) {

241

242 if (hasV8MBaselineOps())

243 NoMovt = false;

244 if (!hasV6MOps())

245 report_fatal_error("Cannot generate execute-only code for this target");

246 }

247

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256 NoARM = true;

257

258 if (TM.isAAPCS_ABI())

260 if (TM.isAAPCS16_ABI())

262

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283 switch (IT) {

286 break;

289 break;

290 }

291

292

293 const FeatureBitset &Bits = getFeatureBits();

294 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) &&

296 HasNEONForFP = true;

297

301 (Arch == ARM::ArchKind::ARMV6K || Arch == ARM::ArchKind::ARMV6) &&

303 ReserveR9 = true;

304

305

308

309

312 case CortexA5:

313 break;

314 case CortexA7:

316 break;

317 case CortexA8:

319 break;

320 case CortexA9:

323 break;

324 case CortexA12:

325 break;

326 case CortexA15:

330 break;

331 case CortexA17:

332 case CortexA32:

333 case CortexA35:

334 case CortexA53:

335 case CortexA55:

336 case CortexA57:

337 case CortexA72:

338 case CortexA73:

339 case CortexA75:

340 case CortexA76:

341 case CortexA77:

342 case CortexA78:

343 case CortexA78AE:

344 case CortexA78C:

345 case CortexA510:

346 case CortexA710:

347 case CortexR4:

348 case CortexR5:

349 case CortexR7:

350 case CortexM3:

351 case CortexM55:

352 case CortexM7:

353 case CortexM85:

354 case CortexR52:

355 case CortexR52plus:

356 case CortexX1:

357 case CortexX1C:

358 break;

359 case Exynos:

364 break;

365 case Kryo:

366 break;

367 case Krait:

369 break;

370 case NeoverseV1:

371 break;

377 break;

378 }

379}

380

387

394

396 return TM.isGVIndirectSymbol(GV);

397}

398

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410

411

412

414 return false;

415

416

418}

419

421

422

423 return hasMVEIntegerOps();

424}

425

431

433

434

437 return false;

438 if (disablePostRAScheduler())

439 return false;

440

442}

443

446 return false;

447 if (disablePostRAScheduler())

448 return false;

450}

451

459

461

462

463

464 return !NoMovt && hasV8MBaselineOps() &&

466}

467

469

471 return true;

472

473

474 if (!hasV6Ops())

475 return false;

476

477

480}

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496 return 2;

497

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506 return 3;

507

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510 return 1;

511}

512

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521 ARM::GPRRegClass.contains(PhysReg);

522}

523

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547 F.needsUnwindTableEntry() &&

550

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559}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isThumb(const MCSubtargetInfo &STI)

This file describes how to lower LLVM calls to machine code calls.

This file declares the targeting of the Machinelegalizer class for ARM.

This file declares the targeting of the RegisterBankInfo class for ARM.

static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)

static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)

ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...

static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))

ITMode

Definition ARMSubtarget.cpp:53

@ RestrictedIT

Definition ARMSubtarget.cpp:55

@ DefaultIT

Definition ARMSubtarget.cpp:54

#define clEnumValN(ENUMVAL, FLAGNAME, DESC)

ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...

bool shouldSignReturnAddress() const

This class provides the information for the target register banks.

bool useFastISel() const

True if fast-isel is used.

Definition ARMSubtarget.cpp:468

bool isTargetMachO() const

bool IsLittle

IsLittle - The target is Little Endian.

bool useMovt() const

Definition ARMSubtarget.cpp:460

bool enablePostRAScheduler() const override

True for some subtargets at > -O0.

Definition ARMSubtarget.cpp:435

ARMLdStMultipleTiming LdStMultipleTiming

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

const Triple & getTargetTriple() const

unsigned getGPRAllocationOrder(const MachineFunction &MF) const

Definition ARMSubtarget.cpp:482

const RegisterBankInfo * getRegBankInfo() const override

Definition ARMSubtarget.cpp:128

unsigned MaxInterleaveFactor

const ARMBaseTargetMachine & TM

bool isThumb1Only() const

ARMProcFamilyEnum ARMProcFamily

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

bool useDFAforSMS() const override

Definition ARMSubtarget.cpp:432

MCPhysReg getFramePointerReg() const

DenormalMode DM

DM - Denormal mode NEON and VFP RunFast mode are not IEEE 754 compliant, use this field to determine ...

bool isTargetWindows() const

bool enableSubRegLiveness() const override

Check whether this subtarget wants to use subregister liveness.

Definition ARMSubtarget.cpp:420

bool isGVIndirectSymbol(const GlobalValue *GV) const

True if the GV will be accessed via an indirect symbol.

Definition ARMSubtarget.cpp:395

unsigned MVEVectorCostFactor

The cost factor for MVE instructions, representing the multiple beats an.

const ARMTargetLowering * getTargetLowering() const override

ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false, DenormalMode DM=DenormalMode::getIEEE())

This constructor initializes the data members to match that of the specified triple.

Definition ARMSubtarget.cpp:88

MCSchedModel SchedModel

SchedModel - Processor specific instruction costs.

std::string CPUString

CPUString - String name of used CPU.

unsigned getMispredictionPenalty() const

Definition ARMSubtarget.cpp:403

unsigned PreferBranchLogAlignment

What alignment is preferred for loop bodies and functions, in log2(bytes).

void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override

Definition ARMSubtarget.cpp:132

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

bool enableMachineScheduler() const override

Returns true if machine scheduler should be enabled.

Definition ARMSubtarget.cpp:407

bool isTargetDarwin() const

const ARMBaseRegisterInfo * getRegisterInfo() const override

InstrItineraryData InstrItins

Selected instruction itineraries (one entry per itinerary class.)

bool useStride4VFPs() const

Definition ARMSubtarget.cpp:452

bool OptMinSize

OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.

bool RestrictIT

RestrictIT - If true, the subtarget disallows generation of complex IT blocks.

bool ignoreCSRForAllocationOrder(const MachineFunction &MF, MCRegister PhysReg) const override

Definition ARMSubtarget.cpp:513

bool isROPI() const

Definition ARMSubtarget.cpp:381

Align stackAlignment

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...

unsigned PartialUpdateClearance

Clearance before partial register updates (in number of instructions)

bool enableMachinePipeliner() const override

Returns true if machine pipeliner should be enabled.

Definition ARMSubtarget.cpp:426

bool enablePostRAMachineScheduler() const override

True for some subtargets at > -O0.

Definition ARMSubtarget.cpp:444

InstructionSelector * getInstructionSelector() const override

Definition ARMSubtarget.cpp:120

bool isXRaySupported() const override

Definition ARMSubtarget.cpp:202

const CallLowering * getCallLowering() const override

Definition ARMSubtarget.cpp:116

enum PushPopSplitVariation getPushPopSplitVariation(const MachineFunction &MF) const

Definition ARMSubtarget.cpp:525

ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...

Definition ARMSubtarget.cpp:73

PushPopSplitVariation

How the push and pop instructions of callee saved general-purpose registers should be split.

@ SplitR11WindowsSEH

When the stack frame size is not known (because of variable-sized objects or realignment),...

@ SplitR7

R7 and LR must be adjacent, because R7 is the frame pointer, and must point to a frame record consist...

@ SplitR11AAPCSSignRA

When generating AAPCS-compilant frame chains, R11 is the frame pointer, and must be pushed adjacent t...

@ NoSplit

All GPRs can be pushed in a single instruction.

bool isGVInGOT(const GlobalValue *GV) const

Returns the constant pool modifier needed to access the GV.

Definition ARMSubtarget.cpp:399

bool isTargetWatchABI() const

bool UseMulOps

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...

const TargetOptions & Options

Options passed via command line that could influence the target.

@ DoubleIssueCheckUnalignedAccess

Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.

@ DoubleIssue

Can load/store 2 registers/cycle.

@ SingleIssuePlusExtras

Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

bool useMachinePipeliner() const

bool useMachineScheduler() const

bool isRWPI() const

Definition ARMSubtarget.cpp:388

const LegalizerInfo * getLegalizerInfo() const override

Definition ARMSubtarget.cpp:124

bool isTargetLinux() const

bool SupportsTailCall

SupportsTailCall - True if the OS supports tail call.

int PreISelOperandLatencyAdjustment

The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

Tracks which library functions to use for a particular subtarget.

bool usesWindowsCFI() const

Wrapper class representing physical registers. Should be passed by value.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Holds all the information related to register banks.

StringRef - Represent a constant reference to a string, i.e.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

LLVM_ABI bool FramePointerIsReserved(const MachineFunction &MF) const

FramePointerIsReserved - This returns true if the frame pointer must always either point to a new fra...

Triple - Helper class for working with autoconf configuration names.

LLVM_ABI StringRef getArchName() const

Get the architecture (first) component of the triple.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

std::string ParseARMTriple(const Triple &TT, StringRef CPU)

LLVM_ABI ArchKind parseArch(StringRef Arch)

@ Swift

Calling convention for Swift.

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

DWARFExpression::Operation Op

Represent subnormal handling kind for floating point instruction inputs and outputs.

static constexpr DenormalMode getPreserveSign()