LLVM: llvm::ARMSubtarget Class Reference (original) (raw)

#include "[Target/ARM/ARMSubtarget.h](ARMSubtarget%5F8h%5Fsource.html)"

Public Types
enum ARMLdStMultipleTiming { DoubleIssue, DoubleIssueCheckUnalignedAccess, SingleIssue, SingleIssuePlusExtras }
What kind of timing do load multiple/store multiple instructions have. More...
enum PushPopSplitVariation { NoSplit, SplitR7, SplitR11WindowsSEH, SplitR11AAPCSSignRA }
How the push and pop instructions of callee saved general-purpose registers should be split. More...
Public Member Functions
ARMSubtarget (const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false, DenormalMode DM=DenormalMode::getIEEE())
This constructor initializes the data members to match that of the specified triple.
unsigned getMaxInlineSizeThreshold () const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
unsigned getMaxMemcpyTPInlineSizeThreshold () const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.
void ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
ARMSubtarget & initializeSubtargetDependencies (StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.
const ARMSelectionDAGInfo * getSelectionDAGInfo () const override
const ARMBaseInstrInfo * getInstrInfo () const override
const ARMTargetLowering * getTargetLowering () const override
const ARMFrameLowering * getFrameLowering () const override
const ARMBaseRegisterInfo * getRegisterInfo () const override
const CallLowering * getCallLowering () const override
InstructionSelector * getInstructionSelector () const override
const LegalizerInfo * getLegalizerInfo () const override
const RegisterBankInfo * getRegBankInfo () const override
void initLibcallLoweringInfo (LibcallLoweringInfo &Info) const override
bool hasARMOps () const
bool useNEONForSinglePrecisionFP () const
bool hasVFP2Base () const
bool hasVFP3Base () const
bool hasVFP4Base () const
bool hasFPARMv8Base () const
bool hasAnyDataBarrier () const
bool useMulOps () const
bool useFPVMLx () const
bool useFPVFMx () const
bool useFPVFMx16 () const
bool useFPVFMx64 () const
bool hasBaseDSP () const
bool hasFusion () const
Return true if the CPU supports any kind of instruction fusion.
const Triple & getTargetTriple () const
bool isReadTPSoft () const
bool isTargetAndroid () const
bool isXRaySupported () const override
bool isROPI () const
bool isRWPI () const
bool useMachineScheduler () const
bool useMachinePipeliner () const
bool hasMinSize () const
bool isThumb1Only () const
bool isThumb2 () const
bool isMClass () const
bool isRClass () const
bool isAClass () const
bool isR9Reserved () const
MCPhysReg getFramePointerReg () const
enum PushPopSplitVariation getPushPopSplitVariation (const MachineFunction &MF) const
bool useStride4VFPs () const
bool useMovt () const
bool supportsTailCall () const
bool allowsUnalignedMem () const
bool restrictIT () const
const std::string & getCPUString () const
bool isLittle () const
unsigned getMispredictionPenalty () const
bool enableMachineScheduler () const override
Returns true if machine scheduler should be enabled.
bool enableMachinePipeliner () const override
Returns true if machine pipeliner should be enabled.
bool useDFAforSMS () const override
bool enablePostRAScheduler () const override
True for some subtargets at > -O0.
bool enablePostRAMachineScheduler () const override
True for some subtargets at > -O0.
bool enableSubRegLiveness () const override
Check whether this subtarget wants to use subregister liveness.
bool useAA () const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
const InstrItineraryData * getInstrItineraryData () const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Align getStackAlignment () const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Align getDualLoadStoreAlignment () const
unsigned getMaxInterleaveFactor () const
unsigned getPartialUpdateClearance () const
ARMLdStMultipleTiming getLdStMultipleTiming () const
int getPreISelOperandLatencyAdjustment () const
bool isGVIndirectSymbol (const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool isGVInGOT (const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool useFastISel () const
True if fast-isel is used.
unsigned getReturnOpcode () const
Returns the correct return opcode for the current feature set.
bool allowPositionIndependentMovt () const
Allow movt+movw for PIC global address calculation.
unsigned getPreferBranchLogAlignment () const
unsigned getMVEVectorCostFactor (TargetTransformInfo::TargetCostKind CostKind) const
bool ignoreCSRForAllocationOrder (const MachineFunction &MF, MCRegister PhysReg) const override
unsigned getGPRAllocationOrder (const MachineFunction &MF) const
bool isCortexA5 () const
bool isCortexA7 () const
bool isCortexA8 () const
bool isCortexA9 () const
bool isCortexA15 () const
bool isSwift () const
bool isCortexM3 () const
bool isCortexM55 () const
bool isCortexM7 () const
bool isCortexM85 () const
bool isLikeA9 () const
bool isCortexR5 () const
bool isKrait () const
bool isTargetDarwin () const
bool isTargetIOS () const
bool isTargetWatchOS () const
bool isTargetWatchABI () const
bool isTargetDriverKit () const
bool isTargetFuchsia () const
bool isTargetLinux () const
bool isTargetNetBSD () const
bool isTargetWindows () const
bool isTargetCOFF () const
bool isTargetELF () const
bool isTargetMachO () const
bool isTargetAEABI () const
bool isTargetGNUAEABI () const
bool isTargetMuslAEABI () const
bool isTargetEHABICompatible () const
Protected Types
enum ARMProcFamilyEnum { Others }
enum ARMProcClassEnum { None, AClass, MClass, RClass }
enum ARMArchEnum
Protected Attributes
ARMProcFamilyEnum ARMProcFamily = Others
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcClassEnum ARMProcClass = None
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
ARMArchEnum ARMArch = ARMv4t
ARMArch - ARM architecture.
bool UseMulOps = false
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
bool SupportsTailCall = false
SupportsTailCall - True if the OS supports tail call.
bool RestrictIT = false
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Align stackAlignment = Align(4)
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
std::string CPUString
CPUString - String name of used CPU.
unsigned MaxInterleaveFactor = 1
unsigned PartialUpdateClearance = 0
Clearance before partial register updates (in number of instructions)
ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
int PreISelOperandLatencyAdjustment = 2
The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.
unsigned PreferBranchLogAlignment = 0
What alignment is preferred for loop bodies and functions, in log2(bytes).
unsigned MVEVectorCostFactor = 0
The cost factor for MVE instructions, representing the multiple beats an.
bool OptMinSize = false
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
bool IsLittle
IsLittle - The target is Little Endian.
DenormalMode DM
DM - Denormal mode NEON and VFP RunFast mode are not IEEE 754 compliant, use this field to determine whether to generate NEON/VFP instructions in related function.
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
const TargetOptions & Options
Options passed via command line that could influence the target.
const ARMBaseTargetMachine & TM

Definition at line 48 of file ARMSubtarget.h.

◆ ARMArchEnum

◆ ARMLdStMultipleTiming

What kind of timing do load multiple/store multiple instructions have.

Enumerator
DoubleIssue Can load/store 2 registers/cycle.
DoubleIssueCheckUnalignedAccess Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
SingleIssue Can load/store 1 register/cycle.
SingleIssuePlusExtras Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially also for register writeback.

Definition at line 71 of file ARMSubtarget.h.

◆ ARMProcClassEnum

Enumerator
None
AClass
MClass
RClass

Definition at line 56 of file ARMSubtarget.h.

◆ ARMProcFamilyEnum

◆ PushPopSplitVariation

How the push and pop instructions of callee saved general-purpose registers should be split.

Enumerator
NoSplit All GPRs can be pushed in a single instruction. push {r0-r12, lr} vpush {d8-d15}
SplitR7 R7 and LR must be adjacent, because R7 is the frame pointer, and must point to a frame record consisting of the previous frame pointer and the return address. push {r0-r7, lr} push {r8-r12} vpush {d8-d15} Note that Thumb1 changes this layout when the frame pointer is R11, using a longer sequence of instructions because R11 can't be used by a Thumb1 push instruction. This doesn't currently have a separate enum value, and is handled entriely within Thumb1FrameLowering::emitPrologue.
SplitR11WindowsSEH When the stack frame size is not known (because of variable-sized objects or realignment), Windows SEH requires the callee-saved registers to be stored in three regions, with R11 and LR below the floating-point registers. push {r0-r10, r12} vpush {d8-d15} push {r11, lr}
SplitR11AAPCSSignRA When generating AAPCS-compilant frame chains, R11 is the frame pointer, and must be pushed adjacent to the return address (LR). Normally this isn't a problem, because the only register between them is r12, which is the intra-procedure-call scratch register, so doesn't need to be saved. However, when PACBTI is in use, r12 contains the authentication code, so does need to be saved. This means that we need a separate push for R11 and LR. push {r0-r10, r12} push {r11, lr} vpush {d8-d15}

Definition at line 86 of file ARMSubtarget.h.

This constructor initializes the data members to match that of the specified triple.

Definition at line 88 of file ARMSubtarget.cpp.

References CPUString, llvm::createARMInstructionSelector(), DM, getRegisterInfo(), getTargetLowering(), IsLittle, isThumb(), isThumb1Only(), Options, OptMinSize, TargetTriple, TM, UseFusedMulOps, and UseMulOps.

Referenced by initializeSubtargetDependencies(), and ParseSubtargetFeatures().

◆ allowPositionIndependentMovt()

bool llvm::ARMSubtarget::allowPositionIndependentMovt ( ) const inline

Allow movt+movw for PIC global address calculation.

ELF does not have GOT relocations for movt+movw. ROPI does not use GOT.

Definition at line 490 of file ARMSubtarget.h.

References isROPI(), and isTargetELF().

◆ allowsUnalignedMem()

bool llvm::ARMSubtarget::allowsUnalignedMem ( ) const inline

◆ enableMachinePipeliner()

bool ARMSubtarget::enableMachinePipeliner ( ) const override

◆ enableMachineScheduler()

bool ARMSubtarget::enableMachineScheduler ( ) const override

◆ enablePostRAMachineScheduler()

bool ARMSubtarget::enablePostRAMachineScheduler ( ) const override

◆ enablePostRAScheduler()

bool ARMSubtarget::enablePostRAScheduler ( ) const override

◆ enableSubRegLiveness()

bool ARMSubtarget::enableSubRegLiveness ( ) const override

◆ getCallLowering()

◆ getCPUString()

const std::string & llvm::ARMSubtarget::getCPUString ( ) const inline

◆ getDualLoadStoreAlignment()

Align llvm::ARMSubtarget::getDualLoadStoreAlignment ( ) const inline

◆ getFrameLowering()

◆ getFramePointerReg()

MCPhysReg llvm::ARMSubtarget::getFramePointerReg ( ) const inline

◆ getGPRAllocationOrder()

◆ getInstrInfo()

◆ getInstrItineraryData()

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition at line 441 of file ARMSubtarget.h.

References InstrItins.

◆ getInstructionSelector()

◆ getLdStMultipleTiming()

ARMLdStMultipleTiming llvm::ARMSubtarget::getLdStMultipleTiming ( ) const inline

◆ getLegalizerInfo()

◆ getMaxInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold ( ) const inline

◆ getMaxInterleaveFactor()

unsigned llvm::ARMSubtarget::getMaxInterleaveFactor ( ) const inline

◆ getMaxMemcpyTPInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold ( ) const inline

getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.

This threshold should only be used for constant size inputs.

Definition at line 227 of file ARMSubtarget.h.

Referenced by shouldGenerateInlineTPLoop().

◆ getMispredictionPenalty()

unsigned ARMSubtarget::getMispredictionPenalty ( ) const

◆ getMVEVectorCostFactor()

◆ getPartialUpdateClearance()

unsigned llvm::ARMSubtarget::getPartialUpdateClearance ( ) const inline

◆ getPreferBranchLogAlignment()

unsigned llvm::ARMSubtarget::getPreferBranchLogAlignment ( ) const inline

◆ getPreISelOperandLatencyAdjustment()

int llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment ( ) const inline

◆ getPushPopSplitVariation()

Definition at line 525 of file ARMSubtarget.cpp.

References F, llvm::TargetOptions::FramePointerIsReserved(), llvm::MachineFunction::getFrameInfo(), getFramePointerReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), getRegisterInfo(), llvm::MachineFunction::getTarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), isThumb1Only(), NoSplit, llvm::TargetMachine::Options, llvm::ARMFunctionInfo::shouldSignReturnAddress(), SplitR11AAPCSSignRA, SplitR11WindowsSEH, SplitR7, and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), and getMaxFPOffset().

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getReturnOpcode()

unsigned llvm::ARMSubtarget::getReturnOpcode ( ) const inline

Returns the correct return opcode for the current feature set.

Use BX if available to allow mixing thumb/arm code, but fall back to plain mov pc,lr on ARMv4.

Definition at line 479 of file ARMSubtarget.h.

References isThumb().

◆ getSelectionDAGInfo()

◆ getStackAlignment()

Align llvm::ARMSubtarget::getStackAlignment ( ) const inline

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 448 of file ARMSubtarget.h.

References stackAlignment.

◆ getTargetLowering()

◆ getTargetTriple()

const Triple & llvm::ARMSubtarget::getTargetTriple ( ) const inline

◆ hasAnyDataBarrier()

bool llvm::ARMSubtarget::hasAnyDataBarrier ( ) const inline

◆ hasARMOps()

bool llvm::ARMSubtarget::hasARMOps ( ) const inline

◆ hasBaseDSP()

bool llvm::ARMSubtarget::hasBaseDSP ( ) const inline

◆ hasFPARMv8Base()

bool llvm::ARMSubtarget::hasFPARMv8Base ( ) const inline

◆ hasFusion()

bool llvm::ARMSubtarget::hasFusion ( ) const inline

Return true if the CPU supports any kind of instruction fusion.

Definition at line 335 of file ARMSubtarget.h.

◆ hasMinSize()

bool llvm::ARMSubtarget::hasMinSize ( ) const inline

◆ hasVFP2Base()

bool llvm::ARMSubtarget::hasVFP2Base ( ) const inline

◆ hasVFP3Base()

bool llvm::ARMSubtarget::hasVFP3Base ( ) const inline

◆ hasVFP4Base()

bool llvm::ARMSubtarget::hasVFP4Base ( ) const inline

◆ ignoreCSRForAllocationOrder()

◆ initializeSubtargetDependencies()

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.

Definition at line 73 of file ARMSubtarget.cpp.

References ARMSubtarget().

◆ initLibcallLoweringInfo()

◆ isAClass()

bool llvm::ARMSubtarget::isAClass ( ) const inline

◆ isCortexA15()

bool llvm::ARMSubtarget::isCortexA15 ( ) const inline

◆ isCortexA5()

bool llvm::ARMSubtarget::isCortexA5 ( ) const inline

These functions are obsolete, please consider adding subtarget features or properties instead of calling them.

Definition at line 290 of file ARMSubtarget.h.

References ARMProcFamily.

◆ isCortexA7()

bool llvm::ARMSubtarget::isCortexA7 ( ) const inline

◆ isCortexA8()

bool llvm::ARMSubtarget::isCortexA8 ( ) const inline

◆ isCortexA9()

bool llvm::ARMSubtarget::isCortexA9 ( ) const inline

◆ isCortexM3()

bool llvm::ARMSubtarget::isCortexM3 ( ) const inline

◆ isCortexM55()

bool llvm::ARMSubtarget::isCortexM55 ( ) const inline

◆ isCortexM7()

bool llvm::ARMSubtarget::isCortexM7 ( ) const inline

◆ isCortexM85()

bool llvm::ARMSubtarget::isCortexM85 ( ) const inline

◆ isCortexR5()

bool llvm::ARMSubtarget::isCortexR5 ( ) const inline

◆ isGVIndirectSymbol()

True if the GV will be accessed via an indirect symbol.

Definition at line 395 of file ARMSubtarget.cpp.

References TM.

◆ isGVInGOT()

◆ isKrait()

bool llvm::ARMSubtarget::isKrait ( ) const inline

◆ isLikeA9()

bool llvm::ARMSubtarget::isLikeA9 ( ) const inline

◆ isLittle()

bool llvm::ARMSubtarget::isLittle ( ) const inline

◆ isMClass()

bool llvm::ARMSubtarget::isMClass ( ) const inline

◆ isR9Reserved()

bool llvm::ARMSubtarget::isR9Reserved ( ) const inline

◆ isRClass()

bool llvm::ARMSubtarget::isRClass ( ) const inline

◆ isReadTPSoft()

bool llvm::ARMSubtarget::isReadTPSoft ( ) const inline

◆ isROPI()

bool ARMSubtarget::isROPI ( ) const

◆ isRWPI()

bool ARMSubtarget::isRWPI ( ) const

◆ isSwift()

bool llvm::ARMSubtarget::isSwift ( ) const inline

◆ isTargetAEABI()

bool llvm::ARMSubtarget::isTargetAEABI ( ) const inline

◆ isTargetAndroid()

bool llvm::ARMSubtarget::isTargetAndroid ( ) const inline

◆ isTargetCOFF()

bool llvm::ARMSubtarget::isTargetCOFF ( ) const inline

◆ isTargetDarwin()

bool llvm::ARMSubtarget::isTargetDarwin ( ) const inline

◆ isTargetDriverKit()

bool llvm::ARMSubtarget::isTargetDriverKit ( ) const inline

◆ isTargetEHABICompatible()

bool llvm::ARMSubtarget::isTargetEHABICompatible ( ) const inline

◆ isTargetELF()

bool llvm::ARMSubtarget::isTargetELF ( ) const inline

◆ isTargetFuchsia()

bool llvm::ARMSubtarget::isTargetFuchsia ( ) const inline

◆ isTargetGNUAEABI()

bool llvm::ARMSubtarget::isTargetGNUAEABI ( ) const inline

◆ isTargetIOS()

bool llvm::ARMSubtarget::isTargetIOS ( ) const inline

◆ isTargetLinux()

bool llvm::ARMSubtarget::isTargetLinux ( ) const inline

◆ isTargetMachO()

bool llvm::ARMSubtarget::isTargetMachO ( ) const inline

◆ isTargetMuslAEABI()

bool llvm::ARMSubtarget::isTargetMuslAEABI ( ) const inline

◆ isTargetNetBSD()

bool llvm::ARMSubtarget::isTargetNetBSD ( ) const inline

◆ isTargetWatchABI()

bool llvm::ARMSubtarget::isTargetWatchABI ( ) const inline

◆ isTargetWatchOS()

bool llvm::ARMSubtarget::isTargetWatchOS ( ) const inline

◆ isTargetWindows()

bool llvm::ARMSubtarget::isTargetWindows ( ) const inline

◆ isThumb1Only()

bool llvm::ARMSubtarget::isThumb1Only ( ) const inline

Definition at line 383 of file ARMSubtarget.h.

References isThumb().

Referenced by ARMSubtarget(), attachMEMCPYScratchRegs(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::emitJumpTableTBInst(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enablePostRAMachineScheduler(), enablePostRAScheduler(), getGPRAllocationOrder(), getPushPopSplitVariation(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), LowerADDSUBSAT(), llvm::ARMCallLowering::lowerCall(), LowerPREFETCH(), LowerSTORE(), PerformAddcSubcCombine(), PerformADDECombine(), PerformAddeSubeCombine(), PerformANDCombine(), PerformMULCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformXORCombine(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), useFastISel(), and llvm::ThumbRegisterInfo::useFPForScavengingIndex().

◆ isThumb2()

bool llvm::ARMSubtarget::isThumb2 ( ) const inline

◆ isXRaySupported()

bool ARMSubtarget::isXRaySupported ( ) const override

◆ ParseSubtargetFeatures()

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

References ARMSubtarget().

◆ restrictIT()

bool llvm::ARMSubtarget::restrictIT ( ) const inline

◆ supportsTailCall()

bool llvm::ARMSubtarget::supportsTailCall ( ) const inline

◆ useAA()

bool llvm::ARMSubtarget::useAA ( ) const inlineoverride

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 437 of file ARMSubtarget.h.

◆ useDFAforSMS()

bool ARMSubtarget::useDFAforSMS ( ) const override

◆ useFastISel()

bool ARMSubtarget::useFastISel ( ) const

◆ useFPVFMx()

bool llvm::ARMSubtarget::useFPVFMx ( ) const inline

◆ useFPVFMx16()

bool llvm::ARMSubtarget::useFPVFMx16 ( ) const inline

◆ useFPVFMx64()

bool llvm::ARMSubtarget::useFPVFMx64 ( ) const inline

◆ useFPVMLx()

bool llvm::ARMSubtarget::useFPVMLx ( ) const inline

◆ useMachinePipeliner()

bool llvm::ARMSubtarget::useMachinePipeliner ( ) const inline

◆ useMachineScheduler()

bool llvm::ARMSubtarget::useMachineScheduler ( ) const inline

◆ useMovt()

bool ARMSubtarget::useMovt ( ) const

◆ useMulOps()

bool llvm::ARMSubtarget::useMulOps ( ) const inline

◆ useNEONForSinglePrecisionFP()

bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP ( ) const inline

◆ useStride4VFPs()

bool ARMSubtarget::useStride4VFPs ( ) const

◆ ARMArch

ARMArchEnum llvm::ARMSubtarget::ARMArch = ARMv4t protected

◆ ARMProcClass

ARMProcClassEnum llvm::ARMSubtarget::ARMProcClass = None protected

◆ ARMProcFamily

ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily = Others protected

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition at line 133 of file ARMSubtarget.h.

Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexM55(), isCortexM7(), isCortexM85(), isCortexR5(), isKrait(), and isSwift().

◆ CPUString

std::string llvm::ARMSubtarget::CPUString protected

◆ DM

DM - Denormal mode NEON and VFP RunFast mode are not IEEE 754 compliant, use this field to determine whether to generate NEON/VFP instructions in related function.

Definition at line 193 of file ARMSubtarget.h.

Referenced by ARMSubtarget().

◆ InstrItins

◆ IsLittle

bool llvm::ARMSubtarget::IsLittle protected

◆ LdStMultipleTiming

ARMLdStMultipleTiming llvm::ARMSubtarget::LdStMultipleTiming = SingleIssue protected

◆ MaxInterleaveFactor

unsigned llvm::ARMSubtarget::MaxInterleaveFactor = 1 protected

◆ MVEVectorCostFactor

unsigned llvm::ARMSubtarget::MVEVectorCostFactor = 0 protected

◆ Options

◆ OptMinSize

bool llvm::ARMSubtarget::OptMinSize = false protected

◆ PartialUpdateClearance

unsigned llvm::ARMSubtarget::PartialUpdateClearance = 0 protected

◆ PreferBranchLogAlignment

unsigned llvm::ARMSubtarget::PreferBranchLogAlignment = 0 protected

◆ PreISelOperandLatencyAdjustment

int llvm::ARMSubtarget::PreISelOperandLatencyAdjustment = 2 protected

◆ RestrictIT

bool llvm::ARMSubtarget::RestrictIT = false protected

RestrictIT - If true, the subtarget disallows generation of complex IT blocks.

Definition at line 152 of file ARMSubtarget.h.

Referenced by restrictIT().

◆ SchedModel

◆ stackAlignment

Align llvm::ARMSubtarget::stackAlignment = Align(4) protected

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 156 of file ARMSubtarget.h.

Referenced by getStackAlignment().

◆ SupportsTailCall

bool llvm::ARMSubtarget::SupportsTailCall = false protected

SupportsTailCall - True if the OS supports tail call.

The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.

Definition at line 148 of file ARMSubtarget.h.

Referenced by supportsTailCall().

◆ TargetTriple

Triple llvm::ARMSubtarget::TargetTriple protected

TargetTriple - What processor and OS we're targeting.

Definition at line 196 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), getTargetTriple(), isTargetAEABI(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetDriverKit(), isTargetEHABICompatible(), isTargetELF(), isTargetFuchsia(), isTargetGNUAEABI(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetMuslAEABI(), isTargetNetBSD(), isTargetWatchABI(), isTargetWatchOS(), and isTargetWindows().

◆ TM

◆ UseMulOps

bool llvm::ARMSubtarget::UseMulOps = false protected

The documentation for this class was generated from the following files: