ARMSubtarget.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H

14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H

35#include

36#include

37#include

39#define GET_SUBTARGETINFO_HEADER

40#include "ARMGenSubtargetInfo.inc"

42namespace llvm {

44class ARMBaseTargetMachine;

45class GlobalValue;

46class StringRef;

49protected:

52#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,

53#include "llvm/TargetParser/ARMTargetParserDef.inc"

54#undef ARM_PROCESSOR_FAMILY

55 };

64#define ARM_ARCHITECTURE(ENUM) ENUM,

65#include "llvm/TargetParser/ARMTargetParserDef.inc"

66#undef ARM_ARCHITECTURE

67 };

69public:

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124 };

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126protected:

127

128#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

129 bool ATTRIBUTE = DEFAULT;

130#include "ARMGenSubtargetInfo.inc"

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209public:

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213 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,

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238 return &TSInfo;

239 }

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242 return InstrInfo.get();

243 }

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246 return &TLInfo;

247 }

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250 return FrameLowering.get();

251 }

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254 return &InstrInfo->getRegisterInfo();

255 }

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263private:

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266 std::unique_ptr FrameLowering;

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268 std::unique_ptr InstrInfo;

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272 std::unique_ptr CallLoweringInfo;

273 std::unique_ptr InstSelector;

274 std::unique_ptr Legalizer;

275 std::unique_ptr RegBankInfo;

276

279

280 std::bitset<8> CoprocCDE = {};

281public:

282

283#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

284 bool GETTER() const { return ATTRIBUTE; }

285#include "ARMGenSubtargetInfo.inc"

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308 return hasNEON() && hasNEONForFP();

309 }

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317 return HasDataBarrier || (hasV6Ops() && isThumb ());

318 }

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321 bool useFPVMLx() const { return !SlowFPVMLx; }

329 return hasThumb2() && hasDSP();

330 else

331 return hasV5TEOps();

332 }

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335 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }

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370 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());

371 }

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390 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;

391 }

392

396 return ARM::R7;

397 return ARM::R11;

398 }

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437 bool useAA() const override { return true; }

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481 return ARM::tBX_RET;

482 if (hasV4TOps())

483 return ARM::BX_RET;

484 return ARM::MOVPCLR;

485 }

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498 unsigned

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508};

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510}

511

512#endif

static bool isThumb(const MCSubtargetInfo &STI)

Analysis containing CSE Info

This file describes how to lower LLVM calls to machine code calls.

static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))

Interface for Targets to specify which operations they can successfully select and how the others sho...

This pass exposes codegen information to IR-level passes.

bool useFastISel() const

True if fast-isel is used.

ARMProcClassEnum

Definition ARMSubtarget.h:56

@ AClass

Definition ARMSubtarget.h:59

@ None

Definition ARMSubtarget.h:57

@ MClass

Definition ARMSubtarget.h:60

@ RClass

Definition ARMSubtarget.h:61

bool isTargetMachO() const

Definition ARMSubtarget.h:354

bool hasFusion() const

Return true if the CPU supports any kind of instruction fusion.

Definition ARMSubtarget.h:335

bool isCortexA7() const

Definition ARMSubtarget.h:291

bool IsLittle

IsLittle - The target is Little Endian.

Definition ARMSubtarget.h:187

bool isSwift() const

Definition ARMSubtarget.h:295

bool isTargetAEABI() const

Definition ARMSubtarget.h:356

bool enablePostRAScheduler() const override

True for some subtargets at > -O0.

ARMLdStMultipleTiming LdStMultipleTiming

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

Definition ARMSubtarget.h:168

bool hasARMOps() const

Definition ARMSubtarget.h:305

bool supportsTailCall() const

Definition ARMSubtarget.h:407

const Triple & getTargetTriple() const

Definition ARMSubtarget.h:337

ARMProcFamilyEnum

Definition ARMSubtarget.h:50

@ Others

Definition ARMSubtarget.h:51

bool hasVFP4Base() const

Definition ARMSubtarget.h:313

unsigned getGPRAllocationOrder(const MachineFunction &MF) const

const RegisterBankInfo * getRegBankInfo() const override

unsigned MaxInterleaveFactor

Definition ARMSubtarget.h:161

const ARMBaseTargetMachine & TM

Definition ARMSubtarget.h:207

bool isRClass() const

Definition ARMSubtarget.h:386

ARMLdStMultipleTiming getLdStMultipleTiming() const

Definition ARMSubtarget.h:459

const ARMBaseInstrInfo * getInstrInfo() const override

Definition ARMSubtarget.h:241

bool useFPVMLx() const

Definition ARMSubtarget.h:321

bool isCortexM85() const

Definition ARMSubtarget.h:299

bool isThumb1Only() const

Definition ARMSubtarget.h:383

ARMProcFamilyEnum ARMProcFamily

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition ARMSubtarget.h:133

bool useFPVFMx() const

Definition ARMSubtarget.h:322

ARMArchEnum ARMArch

ARMArch - ARM architecture.

Definition ARMSubtarget.h:139

bool isCortexM7() const

Definition ARMSubtarget.h:298

bool hasFPARMv8Base() const

Definition ARMSubtarget.h:314

bool isAClass() const

Definition ARMSubtarget.h:387

bool isThumb2() const

Definition ARMSubtarget.h:384

bool useDFAforSMS() const override

bool isReadTPSoft() const

Definition ARMSubtarget.h:369

ARMProcClassEnum ARMProcClass

ARMProcClass - ARM processor class: None, AClass, RClass or MClass.

Definition ARMSubtarget.h:136

MCPhysReg getFramePointerReg() const

Definition ARMSubtarget.h:393

DenormalMode DM

DM - Denormal mode NEON and VFP RunFast mode are not IEEE 754 compliant, use this field to determine ...

Definition ARMSubtarget.h:193

bool isTargetWindows() const

Definition ARMSubtarget.h:350

bool isTargetEHABICompatible() const

Definition ARMSubtarget.h:364

bool isCortexR5() const

Definition ARMSubtarget.h:301

bool enableSubRegLiveness() const override

Check whether this subtarget wants to use subregister liveness.

bool isGVIndirectSymbol(const GlobalValue *GV) const

True if the GV will be accessed via an indirect symbol.

unsigned MVEVectorCostFactor

The cost factor for MVE instructions, representing the multiple beats an.

Definition ARMSubtarget.h:180

bool hasBaseDSP() const

Definition ARMSubtarget.h:327

const ARMTargetLowering * getTargetLowering() const override

Definition ARMSubtarget.h:245

ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false, DenormalMode DM=DenormalMode::getIEEE())

This constructor initializes the data members to match that of the specified triple.

MCSchedModel SchedModel

SchedModel - Processor specific instruction costs.

Definition ARMSubtarget.h:199

std::string CPUString

CPUString - String name of used CPU.

Definition ARMSubtarget.h:159

unsigned getMispredictionPenalty() const

unsigned PreferBranchLogAlignment

What alignment is preferred for loop bodies and functions, in log2(bytes).

Definition ARMSubtarget.h:175

void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

Definition ARMSubtarget.h:196

bool enableMachineScheduler() const override

Returns true if machine scheduler should be enabled.

bool isCortexM55() const

Definition ARMSubtarget.h:297

bool isLikeA9() const

Definition ARMSubtarget.h:300

bool isTargetDarwin() const

Definition ARMSubtarget.h:342

const ARMBaseRegisterInfo * getRegisterInfo() const override

Definition ARMSubtarget.h:253

InstrItineraryData InstrItins

Selected instruction itineraries (one entry per itinerary class.)

Definition ARMSubtarget.h:202

bool useStride4VFPs() const

bool OptMinSize

OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.

Definition ARMSubtarget.h:184

unsigned getReturnOpcode() const

Returns the correct return opcode for the current feature set.

Definition ARMSubtarget.h:479

bool RestrictIT

RestrictIT - If true, the subtarget disallows generation of complex IT blocks.

Definition ARMSubtarget.h:152

Align getStackAlignment() const

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...

Definition ARMSubtarget.h:448

bool isKrait() const

Definition ARMSubtarget.h:302

bool isCortexA5() const

Definition ARMSubtarget.h:290

bool ignoreCSRForAllocationOrder(const MachineFunction &MF, MCRegister PhysReg) const override

bool hasVFP2Base() const

Definition ARMSubtarget.h:311

bool useAA() const override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

Definition ARMSubtarget.h:437

bool isTargetAndroid() const

Definition ARMSubtarget.h:373

Align stackAlignment

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...

Definition ARMSubtarget.h:156

unsigned getMaxMemcpyTPInlineSizeThreshold() const

getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...

Definition ARMSubtarget.h:227

unsigned PartialUpdateClearance

Clearance before partial register updates (in number of instructions)

Definition ARMSubtarget.h:164

bool enableMachinePipeliner() const override

Returns true if machine pipeliner should be enabled.

bool enablePostRAMachineScheduler() const override

True for some subtargets at > -O0.

bool isTargetCOFF() const

Definition ARMSubtarget.h:352

unsigned getMaxInlineSizeThreshold() const

getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...

Definition ARMSubtarget.h:219

bool isTargetGNUAEABI() const

Definition ARMSubtarget.h:358

const ARMSelectionDAGInfo * getSelectionDAGInfo() const override

Definition ARMSubtarget.h:237

const std::string & getCPUString() const

Definition ARMSubtarget.h:413

InstructionSelector * getInstructionSelector() const override

unsigned getMaxInterleaveFactor() const

Definition ARMSubtarget.h:455

bool hasVFP3Base() const

Definition ARMSubtarget.h:312

bool isR9Reserved() const

Definition ARMSubtarget.h:389

bool useFPVFMx64() const

Definition ARMSubtarget.h:326

unsigned getPartialUpdateClearance() const

Definition ARMSubtarget.h:457

bool isTargetNetBSD() const

Definition ARMSubtarget.h:349

bool isTargetWatchOS() const

Definition ARMSubtarget.h:344

bool isXRaySupported() const override

ARMArchEnum

Definition ARMSubtarget.h:63

unsigned getPreferBranchLogAlignment() const

Definition ARMSubtarget.h:494

const CallLowering * getCallLowering() const override

enum PushPopSplitVariation getPushPopSplitVariation(const MachineFunction &MF) const

bool hasMinSize() const

Definition ARMSubtarget.h:382

ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...

PushPopSplitVariation

How the push and pop instructions of callee saved general-purpose registers should be split.

Definition ARMSubtarget.h:86

@ SplitR11WindowsSEH

When the stack frame size is not known (because of variable-sized objects or realignment),...

Definition ARMSubtarget.h:111

@ SplitR7

R7 and LR must be adjacent, because R7 is the frame pointer, and must point to a frame record consist...

Definition ARMSubtarget.h:102

@ SplitR11AAPCSSignRA

When generating AAPCS-compilant frame chains, R11 is the frame pointer, and must be pushed adjacent t...

Definition ARMSubtarget.h:123

@ NoSplit

All GPRs can be pushed in a single instruction.

Definition ARMSubtarget.h:90

bool isTargetIOS() const

Definition ARMSubtarget.h:343

bool isGVInGOT(const GlobalValue *GV) const

Returns the constant pool modifier needed to access the GV.

bool useNEONForSinglePrecisionFP() const

Definition ARMSubtarget.h:307

const InstrItineraryData * getInstrItineraryData() const override

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition ARMSubtarget.h:441

bool isCortexM3() const

Definition ARMSubtarget.h:296

bool isTargetWatchABI() const

Definition ARMSubtarget.h:345

bool allowPositionIndependentMovt() const

Allow movt+movw for PIC global address calculation.

Definition ARMSubtarget.h:490

bool isCortexA8() const

Definition ARMSubtarget.h:292

bool UseMulOps

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...

Definition ARMSubtarget.h:143

const TargetOptions & Options

Options passed via command line that could influence the target.

Definition ARMSubtarget.h:205

ARMLdStMultipleTiming

What kind of timing do load multiple/store multiple instructions have.

Definition ARMSubtarget.h:71

@ DoubleIssueCheckUnalignedAccess

Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.

Definition ARMSubtarget.h:76

@ SingleIssue

Can load/store 1 register/cycle.

Definition ARMSubtarget.h:78

@ DoubleIssue

Can load/store 2 registers/cycle.

Definition ARMSubtarget.h:73

@ SingleIssuePlusExtras

Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...

Definition ARMSubtarget.h:81

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

bool hasAnyDataBarrier() const

Definition ARMSubtarget.h:316

bool useMachinePipeliner() const

Definition ARMSubtarget.h:381

bool isTargetDriverKit() const

Definition ARMSubtarget.h:346

int getPreISelOperandLatencyAdjustment() const

Definition ARMSubtarget.h:463

bool useMachineScheduler() const

Definition ARMSubtarget.h:380

bool isCortexA15() const

Definition ARMSubtarget.h:294

bool isLittle() const

Definition ARMSubtarget.h:415

bool allowsUnalignedMem() const

Definition ARMSubtarget.h:409

bool isTargetMuslAEABI() const

Definition ARMSubtarget.h:360

const LegalizerInfo * getLegalizerInfo() const override

bool isTargetLinux() const

Definition ARMSubtarget.h:348

bool isTargetFuchsia() const

Definition ARMSubtarget.h:347

bool isCortexA9() const

Definition ARMSubtarget.h:293

bool useFPVFMx16() const

Definition ARMSubtarget.h:325

bool isMClass() const

Definition ARMSubtarget.h:385

bool SupportsTailCall

SupportsTailCall - True if the OS supports tail call.

Definition ARMSubtarget.h:148

int PreISelOperandLatencyAdjustment

The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...

Definition ARMSubtarget.h:172

bool useMulOps() const

Definition ARMSubtarget.h:320

bool isTargetELF() const

Definition ARMSubtarget.h:353

bool restrictIT() const

Definition ARMSubtarget.h:411

unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const

Definition ARMSubtarget.h:499

const ARMFrameLowering * getFrameLowering() const override

Definition ARMSubtarget.h:249

Align getDualLoadStoreAlignment() const

Definition ARMSubtarget.h:451

Itinerary data supplied by a subtarget to be used by a target.

Tracks which library functions to use for a particular subtarget.

Wrapper class representing physical registers. Should be passed by value.

Holds all the information related to register banks.

StringRef - Represent a constant reference to a string, i.e.

TargetCostKind

The kind of cost model.

@ TCK_CodeSize

Instruction code size.

Triple - Helper class for working with autoconf configuration names.

@ Swift

Calling convention for Swift.

This is an optimization pass for GlobalISel generic memory operations.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

This struct is a compact representation of a valid (non-zero power of two) alignment.

Represent subnormal handling kind for floating point instruction inputs and outputs.

static constexpr DenormalMode getIEEE()

Machine model for scheduling, bundling, and heuristics.