LLVM: lib/CodeGen/AllocationOrder.cpp Source File (original) (raw)

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24using namespace llvm;

25

26#define DEBUG_TYPE "regalloc"

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36 bool HardHints =

37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);

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40 if (!Hints.empty()) {

41 dbgs() << "hints:";

42 for (MCPhysReg Hint : Hints)

43 dbgs() << ' ' << printReg(Hint, TRI);

44 dbgs() << '\n';

45 }

46 });

49 "Target hint is outside allocation order.");

50 return AllocationOrder(std::move(Hints), Order, HardHints);

51}

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)

Create a new AllocationOrder for VirtReg.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const

getOrder - Returns the preferred allocation order for RC.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

MachineFunction & getMachineFunction() const

const TargetRegisterInfo & getTargetRegInfo() const

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.