Utils.cpp Source File (original) (raw)

38#include

39#include

41#define DEBUG_TYPE "globalisel-utils"

43using namespace llvm;

51 return MRI.createVirtualRegister(&RegClass);

53 return Reg;

54}

63 assert(Reg.isVirtual() && "PhysReg not implemented");

69 auto *OldRegClass = MRI.getRegClassOrNull(Reg);

73 if (ConstrainedReg != Reg) {

78 if (RegMO.isUse()) {

80 TII.get(TargetOpcode::COPY), ConstrainedReg)

82 } else {

83 assert(RegMO.isDef() && "Must be a definition");

85 TII.get(TargetOpcode::COPY), Reg)

86 .addReg(ConstrainedReg);

87 }

89 Observer->changingInstr(*RegMO.getParent());

90 }

91 RegMO.setReg(ConstrainedReg);

93 Observer->changedInstr(*RegMO.getParent());

94 }

95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {

97 if (!RegMO.isDef()) {

99 Observer->changedInstr(*RegDef);

100 }

101 Observer->changingAllUsesOfReg(MRI, Reg);

102 Observer->finishedChangingAllUsesOfReg();

103 }

104 }

105 return ConstrainedReg;

106}

107

114

115 assert(Reg.isVirtual() && "PhysReg not implemented");

116

118

119

120

121

122

123 if (OpRC) {

124

125

126

127

128 if (const auto *SubRC = TRI.getCommonSubClass(

129 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))

130 OpRC = SubRC;

131

132 OpRC = TRI.getAllocatableClass(OpRC);

133 }

134

135 if (!OpRC) {

137 "Register class constraint is required unless either the "

138 "instruction is target independent or the operand is a use");

139

140

141

142

143

144

145

146

147

148

149 return Reg;

150 }

152 RegMO);

153}

154

160 "A selected instruction is expected");

164

165 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {

167

168

170 continue;

171

172 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');

173 assert(MO.isReg() && "Unsupported non-reg operand");

174

176

177 if (Reg.isPhysical())

178 continue;

179

180

181

182 if (Reg == 0)

183 continue;

184

185

186

187

189

190

191

192 if (MO.isUse()) {

193 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);

194 if (DefIdx != -1 && .isRegTiedToUseOperand(DefIdx))

195 I.tieOperands(DefIdx, OpI);

196 }

197 }

198 return true;

199}

200

203

205 return false;

206

207 if (MRI.getType(DstReg) != MRI.getType(SrcReg))

208 return false;

209

210

211 const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);

212 if (!DstRBC || DstRBC == MRI.getRegClassOrRegBank(SrcReg))

213 return true;

214

215

216

219 *MRI.getRegClassOrNull(SrcReg));

220}

221

224

225

226

227 for (const auto &MO : MI.all_defs()) {

229 if (Reg.isPhysical() || MRI .use_nodbg_empty(Reg))

230 return false;

231 }

232 return MI.wouldBeTriviallyDead();

233}

234

239 bool IsGlobalISelAbortEnabled =

241 bool IsFatal = Severity == DS_Error && IsGlobalISelAbortEnabled;

242

243

244 if (!R.getLocation().isValid() || IsFatal)

245 R << (" (in function: " + MF.getName() + ")").str();

246

247 if (IsFatal)

249 else

250 MORE.emit(R);

251}

252

258

265

271 MI.getDebugLoc(), MI.getParent());

272 R << Msg;

273

278}

279

281 switch (MinMaxOpc) {

282 case TargetOpcode::G_SMIN:

283 return TargetOpcode::G_SMAX;

284 case TargetOpcode::G_SMAX:

285 return TargetOpcode::G_SMIN;

286 case TargetOpcode::G_UMIN:

287 return TargetOpcode::G_UMAX;

288 case TargetOpcode::G_UMAX:

289 return TargetOpcode::G_UMIN;

290 default:

292 }

293}

294

298 VReg, MRI, false);

299 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&

300 "Value found while looking through instrs");

301 if (!ValAndVReg)

302 return std::nullopt;

303 return ValAndVReg->Value;

304}

305

309 assert((Const && Const->getOpcode() == TargetOpcode::G_CONSTANT) &&

310 "expected a G_CONSTANT on Reg");

311 return Const->getOperand(1).getCImm()->getValue();

312}

313

314std::optional<int64_t>

317 if (Val && Val->getBitWidth() <= 64)

318 return Val->getSExtValue();

319 return std::nullopt;

320}

321

322namespace {

323

324

325

326

327

328

329

330

331

332

333

336std::optional

338 bool LookThroughInstrs = true,

339 bool LookThroughAnyExt = false) {

342

343 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&

344 LookThroughInstrs) {

345 switch (MI->getOpcode()) {

346 case TargetOpcode::G_ANYEXT:

347 if (!LookThroughAnyExt)

348 return std::nullopt;

349 [[fallthrough]];

350 case TargetOpcode::G_TRUNC:

351 case TargetOpcode::G_SEXT:

352 case TargetOpcode::G_ZEXT:

353 SeenOpcodes.push_back(std::make_pair(

354 MI->getOpcode(),

355 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));

356 VReg = MI->getOperand(1).getReg();

357 break;

358 case TargetOpcode::COPY:

359 VReg = MI->getOperand(1).getReg();

361 return std::nullopt;

362 break;

363 case TargetOpcode::G_INTTOPTR:

364 VReg = MI->getOperand(1).getReg();

365 break;

366 default:

367 return std::nullopt;

368 }

369 }

370 if ( || !IsConstantOpcode(MI))

371 return std::nullopt;

372

374 if (!GetAPCstValue(MI, Val))

375 return std::nullopt;

376 for (auto &Pair : reverse(SeenOpcodes)) {

377 switch (Pair.first) {

378 case TargetOpcode::G_TRUNC:

379 Val = Val.trunc(Pair.second);

380 break;

381 case TargetOpcode::G_ANYEXT:

382 case TargetOpcode::G_SEXT:

383 Val = Val.sext(Pair.second);

384 break;

385 case TargetOpcode::G_ZEXT:

386 Val = Val.zext(Pair.second);

387 break;

388 }

389 }

390

392}

393

395 if ()

396 return false;

397 return MI->getOpcode() == TargetOpcode::G_CONSTANT;

398}

399

401 if ()

402 return false;

403 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;

404}

405

407 if ()

408 return false;

409 unsigned Opc = MI->getOpcode();

410 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;

411}

412

415 if (!CstVal.isCImm())

416 return false;

418 return true;

419}

420

425 else if (CstVal.isFPImm())

427 else

428 return false;

429 return true;

430}

431

432}

433

436 return getConstantVRegValWithLookThrough<isIConstant, getCImmAsAPInt>(

437 VReg, MRI, LookThroughInstrs);

438}

439

442 bool LookThroughAnyExt) {

443 return getConstantVRegValWithLookThrough<isAnyConstant,

444 getCImmOrFPImmAsAPInt>(

445 VReg, MRI, LookThroughInstrs, LookThroughAnyExt);

446}

447

450 auto Reg =

451 getConstantVRegValWithLookThrough<isFConstant, getCImmOrFPImmAsAPInt>(

452 VReg, MRI, LookThroughInstrs);

453 if (!Reg)

454 return std::nullopt;

456 Reg->VReg};

457}

458

462 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())

463 return nullptr;

464 return MI->getOperand(1).getFPImm();

465}

466

467std::optional

470

471

472 auto DefIt = MRI.def_begin(Reg);

473 if (DefIt == MRI.def_end())

474 return {};

477 auto DstTy = MRI.getType(DefOpnd.getReg());

478 if (!DstTy.isValid())

479 return std::nullopt;

480 unsigned Opc = DefMI->getOpcode();

483 auto SrcTy = MRI.getType(SrcReg);

484 if (!SrcTy.isValid())

485 break;

486 DefMI = MRI.getVRegDef(SrcReg);

487 DefSrcReg = SrcReg;

489 }

491}

492

495 std::optional DefSrcReg =

497 return DefSrcReg ? DefSrcReg->MI : nullptr;

498}

499

502 std::optional DefSrcReg =

504 return DefSrcReg ? DefSrcReg->Reg : Register();

505}

506

511 for (int i = 0; i < NumParts; ++i)

512 VRegs.push_back(MRI.createGenericVirtualRegister(Ty));

514}

515

521 assert(!LeftoverTy.isValid() && "this is an out argument");

522

525 unsigned NumParts = RegSize / MainSize;

526 unsigned LeftoverSize = RegSize - NumParts * MainSize;

527

528

529 if (LeftoverSize == 0) {

530 for (unsigned I = 0; I < NumParts; ++I)

531 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));

533 return true;

534 }

535

536

537

538

539

540

544 unsigned LeftoverNumElts = RegNumElts % MainNumElts;

545

546 if (MainNumElts % LeftoverNumElts == 0 &&

547 RegNumElts % LeftoverNumElts == 0 &&

549 LeftoverNumElts > 1) {

551

552

554 extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues,

555 MIRBuilder, MRI);

556

557

558 unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts;

559 unsigned NumOfLeftoverVal =

560 ((RegNumElts % MainNumElts) / LeftoverNumElts);

561

562

564 for (unsigned I = 0; I < UnmergeValues.size() - NumOfLeftoverVal; I++) {

565 MergeValues.push_back(UnmergeValues[I]);

566 if (MergeValues.size() == LeftoverPerMain) {

569 MergeValues.clear();

570 }

571 }

572

573 for (unsigned I = UnmergeValues.size() - NumOfLeftoverVal;

574 I < UnmergeValues.size(); I++) {

575 LeftoverRegs.push_back(UnmergeValues[I]);

576 }

577 return true;

578 }

579 }

580

585 for (unsigned i = 0; i < RegPieces.size() - 1; ++i)

587 LeftoverRegs.push_back(RegPieces[RegPieces.size() - 1]);

588 LeftoverTy = MRI.getType(LeftoverRegs[0]);

589 return true;

590 }

591

593

594 for (unsigned I = 0; I != NumParts; ++I) {

595 Register NewReg = MRI.createGenericVirtualRegister(MainTy);

597 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);

598 }

599

601 Offset += LeftoverSize) {

602 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);

605 }

606

607 return true;

608}

609

614 LLT RegTy = MRI.getType(Reg);

615 assert(RegTy.isVector() && "Expected a vector type");

616

620 unsigned LeftoverNumElts = RegNumElts % NumElts;

621 unsigned NumNarrowTyPieces = RegNumElts / NumElts;

622

623

624 if (LeftoverNumElts == 0)

625 return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder,

627

628

629

630

632 extractParts(Reg, EltTy, RegNumElts, Elts, MIRBuilder, MRI);

633

635

636 for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) {

639 }

640

641

642 if (LeftoverNumElts == 1) {

644 } else {

649 }

650}

651

657

659 if (Size == 32)

660 return APFloat(float(Val));

661 if (Size == 64)

663 if (Size != 16)

665 bool Ignored;

668 return APF;

669}

670

676 if (!MaybeOp2Cst)

677 return std::nullopt;

678

680 if (!MaybeOp1Cst)

681 return std::nullopt;

682

683 const APInt &C1 = MaybeOp1Cst->Value;

684 const APInt &C2 = MaybeOp2Cst->Value;

685 switch (Opcode) {

686 default:

687 break;

688 case TargetOpcode::G_ADD:

689 return C1 + C2;

690 case TargetOpcode::G_PTR_ADD:

691

692

694 case TargetOpcode::G_AND:

695 return C1 & C2;

696 case TargetOpcode::G_ASHR:

697 return C1.ashr(C2);

698 case TargetOpcode::G_LSHR:

699 return C1.lshr(C2);

700 case TargetOpcode::G_MUL:

701 return C1 * C2;

702 case TargetOpcode::G_OR:

703 return C1 | C2;

704 case TargetOpcode::G_SHL:

705 return C1 << C2;

706 case TargetOpcode::G_SUB:

707 return C1 - C2;

708 case TargetOpcode::G_XOR:

709 return C1 ^ C2;

710 case TargetOpcode::G_UDIV:

711 if (!C2.getBoolValue())

712 break;

713 return C1.udiv(C2);

714 case TargetOpcode::G_SDIV:

715 if (!C2.getBoolValue())

716 break;

717 return C1.sdiv(C2);

718 case TargetOpcode::G_UREM:

719 if (!C2.getBoolValue())

720 break;

721 return C1.urem(C2);

722 case TargetOpcode::G_SREM:

723 if (!C2.getBoolValue())

724 break;

725 return C1.srem(C2);

726 case TargetOpcode::G_SMIN:

728 case TargetOpcode::G_SMAX:

730 case TargetOpcode::G_UMIN:

732 case TargetOpcode::G_UMAX:

734 }

735

736 return std::nullopt;

737}

738

739std::optional

743 if (!Op2Cst)

744 return std::nullopt;

745

747 if (!Op1Cst)

748 return std::nullopt;

749

752 switch (Opcode) {

753 case TargetOpcode::G_FADD:

755 return C1;

756 case TargetOpcode::G_FSUB:

758 return C1;

759 case TargetOpcode::G_FMUL:

761 return C1;

762 case TargetOpcode::G_FDIV:

764 return C1;

765 case TargetOpcode::G_FREM:

766 C1.mod(C2);

767 return C1;

768 case TargetOpcode::G_FCOPYSIGN:

770 return C1;

771 case TargetOpcode::G_FMINNUM:

773 return std::nullopt;

774 return minnum(C1, C2);

775 case TargetOpcode::G_FMAXNUM:

777 return std::nullopt;

778 return maxnum(C1, C2);

779 case TargetOpcode::G_FMINIMUM:

781 case TargetOpcode::G_FMAXIMUM:

783 case TargetOpcode::G_FMINNUM_IEEE:

784 case TargetOpcode::G_FMAXNUM_IEEE:

785

786

787

788

789 break;

790 default:

791 break;

792 }

793

794 return std::nullopt;

795}

796

802 if (!SrcVec2)

804

806 if (!SrcVec1)

808

810 for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {

811 auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),

812 SrcVec2->getSourceReg(Idx), MRI);

813 if (!MaybeCst)

815 FoldedElements.push_back(*MaybeCst);

816 }

817 return FoldedElements;

818}

819

821 bool SNaN) {

824 return false;

825

827 return true;

828

829

831 return !FPVal->getValueAPF().isNaN() ||

832 (SNaN && !FPVal->getValueAPF().isSignaling());

833 }

834

835 if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {

836 for (const auto &Op : DefMI->uses())

838 return false;

839 return true;

840 }

841

842 switch (DefMI->getOpcode()) {

843 default:

844 break;

845 case TargetOpcode::G_FADD:

846 case TargetOpcode::G_FSUB:

847 case TargetOpcode::G_FMUL:

848 case TargetOpcode::G_FDIV:

849 case TargetOpcode::G_FREM:

850 case TargetOpcode::G_FSIN:

851 case TargetOpcode::G_FCOS:

852 case TargetOpcode::G_FTAN:

853 case TargetOpcode::G_FACOS:

854 case TargetOpcode::G_FASIN:

855 case TargetOpcode::G_FATAN:

856 case TargetOpcode::G_FATAN2:

857 case TargetOpcode::G_FCOSH:

858 case TargetOpcode::G_FSINH:

859 case TargetOpcode::G_FTANH:

860 case TargetOpcode::G_FMA:

861 case TargetOpcode::G_FMAD:

862 if (SNaN)

863 return true;

864

865

866 return false;

867 case TargetOpcode::G_FMINNUM_IEEE:

868 case TargetOpcode::G_FMAXNUM_IEEE: {

869 if (SNaN)

870 return true;

871

872

877 }

878 case TargetOpcode::G_FMINNUM:

879 case TargetOpcode::G_FMAXNUM: {

880

881

884 }

885 }

886

887 if (SNaN) {

888

889

890 switch (DefMI->getOpcode()) {

891 case TargetOpcode::G_FPEXT:

892 case TargetOpcode::G_FPTRUNC:

893 case TargetOpcode::G_FCANONICALIZE:

894 return true;

895 default:

896 return false;

897 }

898 }

899

900 return false;

901}

902

910 }

911

914 return V->getPointerAlignment(M->getDataLayout());

915 }

916

918}

919

927 Register LiveIn = MRI.getLiveInVirtReg(PhysReg);

928 if (LiveIn) {

930 if (Def) {

931

932 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");

933 return LiveIn;

934 }

935

936

937

938

939 } else {

940

941 LiveIn = MF.addLiveIn(PhysReg, &RC);

943 MRI.setType(LiveIn, RegTy);

944 }

945

946 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)

948 if (!EntryMBB.isLiveIn(PhysReg))

950 return LiveIn;

951}

952

957 if (MaybeOp1Cst) {

958 switch (Opcode) {

959 default:

960 break;

961 case TargetOpcode::G_SEXT_INREG: {

962 LLT Ty = MRI.getType(Op1);

963 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());

964 }

965 }

966 }

967 return std::nullopt;

968}

969

974 if (!Val)

975 return Val;

976

978

979 switch (Opcode) {

980 case TargetOpcode::G_SEXT:

981 return Val->sext(DstSize);

982 case TargetOpcode::G_ZEXT:

983 case TargetOpcode::G_ANYEXT:

984

985 return Val->zext(DstSize);

986 default:

987 break;

988 }

989

991}

992

993std::optional

996 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);

999 DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,

1001 return DstVal;

1002 }

1003 return std::nullopt;

1004}

1005

1006std::optional<SmallVector>

1008 std::function<unsigned(APInt)> CB) {

1009 LLT Ty = MRI.getType(Src);

1011 auto tryFoldScalar = [&](Register R) -> std::optional {

1013 if (!MaybeCst)

1014 return std::nullopt;

1015 return CB(*MaybeCst);

1016 };

1017 if (Ty.isVector()) {

1018

1020 if (!BV)

1021 return std::nullopt;

1022 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {

1023 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {

1025 continue;

1026 }

1027 return std::nullopt;

1028 }

1029 return FoldedCTLZs;

1030 }

1031 if (auto MaybeCst = tryFoldScalar(Src)) {

1033 return FoldedCTLZs;

1034 }

1035 return std::nullopt;

1036}

1037

1038std::optional<SmallVector>

1040 unsigned DstScalarSizeInBits, unsigned ExtOp,

1042 assert(ExtOp == TargetOpcode::G_SEXT || ExtOp == TargetOpcode::G_ZEXT ||

1043 ExtOp == TargetOpcode::G_ANYEXT);

1044

1045 const LLT Ty = MRI.getType(Op1);

1046

1047 auto GetICmpResultCst = [&](bool IsTrue) {

1048 if (IsTrue)

1049 return ExtOp == TargetOpcode::G_SEXT

1053 };

1054

1055 auto TryFoldScalar = [&](Register LHS, Register RHS) -> std::optional {

1057 if (!RHSCst)

1058 return std::nullopt;

1060 if (!LHSCst)

1061 return std::nullopt;

1062

1063 switch (Pred) {

1065 return GetICmpResultCst(LHSCst->eq(*RHSCst));

1067 return GetICmpResultCst(LHSCst->ne(*RHSCst));

1069 return GetICmpResultCst(LHSCst->ugt(*RHSCst));

1071 return GetICmpResultCst(LHSCst->uge(*RHSCst));

1073 return GetICmpResultCst(LHSCst->ult(*RHSCst));

1075 return GetICmpResultCst(LHSCst->ule(*RHSCst));

1077 return GetICmpResultCst(LHSCst->sgt(*RHSCst));

1079 return GetICmpResultCst(LHSCst->sge(*RHSCst));

1081 return GetICmpResultCst(LHSCst->slt(*RHSCst));

1083 return GetICmpResultCst(LHSCst->sle(*RHSCst));

1084 default:

1085 return std::nullopt;

1086 }

1087 };

1088

1090

1091 if (Ty.isVector()) {

1092

1095 if (!BV1 || !BV2)

1096 return std::nullopt;

1097 assert(BV1->getNumSources() == BV2->getNumSources() && "Invalid vectors");

1098 for (unsigned I = 0; I < BV1->getNumSources(); ++I) {

1099 if (auto MaybeFold =

1100 TryFoldScalar(BV1->getSourceReg(I), BV2->getSourceReg(I))) {

1102 continue;

1103 }

1104 return std::nullopt;

1105 }

1106 return FoldedICmps;

1107 }

1108

1109 if (auto MaybeCst = TryFoldScalar(Op1, Op2)) {

1111 return FoldedICmps;

1112 }

1113

1114 return std::nullopt;

1115}

1116

1119 std::optional DefSrcReg =

1121 if (!DefSrcReg)

1122 return false;

1123

1125 const LLT Ty = MRI.getType(Reg);

1126

1127 switch (MI.getOpcode()) {

1128 case TargetOpcode::G_CONSTANT: {

1129 unsigned BitWidth = Ty.getScalarSizeInBits();

1130 const ConstantInt *CI = MI.getOperand(1).getCImm();

1132 }

1133 case TargetOpcode::G_SHL: {

1134

1135

1136

1137

1139 if (*ConstLHS == 1)

1140 return true;

1141 }

1142

1143 break;

1144 }

1145 case TargetOpcode::G_LSHR: {

1147 if (ConstLHS->isSignMask())

1148 return true;

1149 }

1150

1151 break;

1152 }

1153 case TargetOpcode::G_BUILD_VECTOR: {

1154

1155

1158 return false;

1159

1160 return true;

1161 }

1162 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {

1163

1164

1165 const unsigned BitWidth = Ty.getScalarSizeInBits();

1168 if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())

1169 return false;

1170 }

1171

1172 return true;

1173 }

1174 default:

1175 break;

1176 }

1177

1178 if (!VT)

1179 return false;

1180

1181

1182

1183

1184

1187}

1188

1192

1195 return OrigTy;

1196

1200

1201

1202

1203

1204

1205

1206

1209 "getLCMType not implemented between fixed and scalable vectors.");

1210

1214

1217 return LLT::vector(Mul.divideCoefficientBy(GCDMinElts),

1219 }

1224 OrigElt);

1225 }

1226

1227

1229 LLT VecTy = OrigTy.isVector() ? OrigTy : TargetTy;

1230 LLT ScalarTy = OrigTy.isVector() ? TargetTy : OrigTy;

1233

1234

1237

1238

1239

1243

1246 OrigEltTy);

1247 }

1248

1249

1252

1254 return OrigTy;

1256 return TargetTy;

1258}

1259

1261

1265 "getCoverTy not implemented between fixed and scalable vectors.");

1266

1267 if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||

1269 return getLCMType(OrigTy, TargetTy);

1270

1273 if (OrigTyNumElts % TargetTyNumElts == 0)

1274 return OrigTy;

1275

1276 unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);

1279}

1280

1283 return OrigTy;

1284

1287

1288

1289

1290

1291

1292

1293

1296 "getGCDType not implemented between fixed and scalable vectors.");

1297

1302 OrigElt);

1303

1304

1307 GCD);

1308

1312 OrigElt);

1313 }

1314

1315

1316

1322 return OrigTy;

1323

1324

1325

1326

1327

1333}

1334

1336 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&

1337 "Only G_SHUFFLE_VECTOR can have a splat index!");

1339 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });

1340

1341

1342

1343 if (FirstDefinedIdx == Mask.end())

1344 return 0;

1345

1346

1347

1348 int SplatValue = *FirstDefinedIdx;

1349 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),

1350 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))

1351 return std::nullopt;

1352

1353 return SplatValue;

1354}

1355

1357 return Opcode == TargetOpcode::G_BUILD_VECTOR ||

1358 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;

1359}

1360

1361namespace {

1362

1363std::optional getAnyConstantSplat(Register VReg,

1365 bool AllowUndef) {

1367 if ()

1368 return std::nullopt;

1369

1370 bool isConcatVectorsOp = MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;

1372 return std::nullopt;

1373

1374 std::optional SplatValAndReg;

1377

1378

1379 auto ElementValAndReg =

1380 isConcatVectorsOp

1381 ? getAnyConstantSplat(Element, MRI, AllowUndef)

1383

1384

1385 if (!ElementValAndReg) {

1387 continue;

1388 return std::nullopt;

1389 }

1390

1391

1392 if (!SplatValAndReg)

1393 SplatValAndReg = ElementValAndReg;

1394

1395

1396 if (SplatValAndReg->Value != ElementValAndReg->Value)

1397 return std::nullopt;

1398 }

1399

1400 return SplatValAndReg;

1401}

1402

1403}

1404

1407 int64_t SplatValue, bool AllowUndef) {

1408 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))

1409 return SplatValAndReg->Value.getSExtValue() == SplatValue;

1410

1411 return false;

1412}

1413

1416 const APInt &SplatValue,

1417 bool AllowUndef) {

1418 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef)) {

1419 if (SplatValAndReg->Value.getBitWidth() < SplatValue.getBitWidth())

1421 SplatValAndReg->Value.sext(SplatValue.getBitWidth()), SplatValue);

1423 SplatValAndReg->Value,

1424 SplatValue.sext(SplatValAndReg->Value.getBitWidth()));

1425 }

1426

1427 return false;

1428}

1429

1432 int64_t SplatValue, bool AllowUndef) {

1434 AllowUndef);

1435}

1436

1439 const APInt &SplatValue,

1440 bool AllowUndef) {

1442 AllowUndef);

1443}

1444

1445std::optional

1447 if (auto SplatValAndReg =

1448 getAnyConstantSplat(Reg, MRI, false)) {

1449 if (std::optional ValAndVReg =

1451 return ValAndVReg->Value;

1452 }

1453

1454 return std::nullopt;

1455}

1456

1457std::optional

1462

1463std::optional<int64_t>

1466 if (auto SplatValAndReg =

1467 getAnyConstantSplat(Reg, MRI, false))

1469 return std::nullopt;

1470}

1471

1472std::optional<int64_t>

1477

1478std::optional

1480 bool AllowUndef) {

1481 if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))

1483 return std::nullopt;

1484}

1485

1488 bool AllowUndef) {

1490}

1491

1494 bool AllowUndef) {

1496}

1497

1498std::optional

1500 unsigned Opc = MI.getOpcode();

1502 return std::nullopt;

1505 auto Reg = MI.getOperand(1).getReg();

1507 [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))

1508 return std::nullopt;

1510}

1511

1514 bool AllowFP = true,

1515 bool AllowOpaqueConstants = true) {

1516 switch (MI.getOpcode()) {

1517 case TargetOpcode::G_CONSTANT:

1518 case TargetOpcode::G_IMPLICIT_DEF:

1519 return true;

1520 case TargetOpcode::G_FCONSTANT:

1521 return AllowFP;

1522 case TargetOpcode::G_GLOBAL_VALUE:

1523 case TargetOpcode::G_FRAME_INDEX:

1524 case TargetOpcode::G_BLOCK_ADDR:

1525 case TargetOpcode::G_JUMP_TABLE:

1526 return AllowOpaqueConstants;

1527 default:

1528 return false;

1529 }

1530}

1531

1534 Register Def = MI.getOperand(0).getReg();

1536 return true;

1538 if (!BV)

1539 return false;

1540 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {

1543 continue;

1544 return false;

1545 }

1546 return true;

1547}

1548

1551 bool AllowFP, bool AllowOpaqueConstants) {

1553 return true;

1554

1556 return false;

1557

1558 const unsigned NumOps = MI.getNumOperands();

1559 for (unsigned I = 1; I != NumOps; ++I) {

1560 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());

1562 return false;

1563 }

1564

1565 return true;

1566}

1567

1568std::optional

1571 Register Def = MI.getOperand(0).getReg();

1573 return C->Value;

1575 if (!MaybeCst)

1576 return std::nullopt;

1577 const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();

1578 return APInt(ScalarSize, *MaybeCst, true);

1579}

1580

1581std::optional

1584 Register Def = MI.getOperand(0).getReg();

1586 return FpConst->Value;

1588 if (!MaybeCstFP)

1589 return std::nullopt;

1590 return MaybeCstFP->Value;

1591}

1592

1595 switch (MI.getOpcode()) {

1596 case TargetOpcode::G_IMPLICIT_DEF:

1597 return AllowUndefs;

1598 case TargetOpcode::G_CONSTANT:

1599 return MI.getOperand(1).getCImm()->isNullValue();

1600 case TargetOpcode::G_FCONSTANT: {

1601 const ConstantFP *FPImm = MI.getOperand(1).getFPImm();

1603 }

1604 default:

1605 if (!AllowUndefs)

1606 return false;

1608 }

1609}

1610

1613 bool AllowUndefs) {

1614 switch (MI.getOpcode()) {

1615 case TargetOpcode::G_IMPLICIT_DEF:

1616 return AllowUndefs;

1617 case TargetOpcode::G_CONSTANT:

1618 return MI.getOperand(1).getCImm()->isAllOnesValue();

1619 default:

1620 if (!AllowUndefs)

1621 return false;

1623 }

1624}

1625

1628 std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {

1629

1631 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)

1632 return Match(nullptr);

1633

1634

1635 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)

1636 return Match(Def->getOperand(1).getCImm());

1637

1638 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)

1639 return false;

1640

1641 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {

1642 Register SrcElt = Def->getOperand(I).getReg();

1644 if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {

1645 if (!Match(nullptr))

1646 return false;

1647 continue;

1648 }

1649

1650 if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||

1652 return false;

1653 }

1654

1655 return true;

1656}

1657

1659 bool IsFP) {

1662 return Val & 0x1;

1664 return Val == 1;

1666 return Val == -1;

1667 }

1669}

1670

1672 bool IsVector, bool IsFP) {

1675 return ~Val & 0x1;

1678 return Val == 0;

1679 }

1681}

1682

1684 bool IsFP) {

1688 return 1;

1690 return -1;

1691 }

1693}

1694

1699 if (Op.isReg() && Op.getReg().isVirtual())

1700 DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));

1701 }

1704 MI.eraseFromParent();

1705 if (LocObserver)

1707}

1708

1715

1716 while (!DeadInstChain.empty()) {

1719 continue;

1721 }

1722}

1723

1728

1730 for (auto &Def : MI.defs()) {

1731 assert(Def.isReg() && "Must be a reg");

1732

1734 for (auto &MOUse : MRI.use_operands(Def.getReg())) {

1736

1737 if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {

1739 }

1740 }

1741

1742 if (!DbgUsers.empty()) {

1744 }

1745 }

1746}

1747

1749 switch (Opc) {

1750 case TargetOpcode::G_FABS:

1751 case TargetOpcode::G_FADD:

1752 case TargetOpcode::G_FCANONICALIZE:

1753 case TargetOpcode::G_FCEIL:

1754 case TargetOpcode::G_FCONSTANT:

1755 case TargetOpcode::G_FCOPYSIGN:

1756 case TargetOpcode::G_FCOS:

1757 case TargetOpcode::G_FDIV:

1758 case TargetOpcode::G_FEXP2:

1759 case TargetOpcode::G_FEXP:

1760 case TargetOpcode::G_FFLOOR:

1761 case TargetOpcode::G_FLOG10:

1762 case TargetOpcode::G_FLOG2:

1763 case TargetOpcode::G_FLOG:

1764 case TargetOpcode::G_FMA:

1765 case TargetOpcode::G_FMAD:

1766 case TargetOpcode::G_FMAXIMUM:

1767 case TargetOpcode::G_FMAXIMUMNUM:

1768 case TargetOpcode::G_FMAXNUM:

1769 case TargetOpcode::G_FMAXNUM_IEEE:

1770 case TargetOpcode::G_FMINIMUM:

1771 case TargetOpcode::G_FMINIMUMNUM:

1772 case TargetOpcode::G_FMINNUM:

1773 case TargetOpcode::G_FMINNUM_IEEE:

1774 case TargetOpcode::G_FMUL:

1775 case TargetOpcode::G_FNEARBYINT:

1776 case TargetOpcode::G_FNEG:

1777 case TargetOpcode::G_FPEXT:

1778 case TargetOpcode::G_FPOW:

1779 case TargetOpcode::G_FPTRUNC:

1780 case TargetOpcode::G_FREM:

1781 case TargetOpcode::G_FRINT:

1782 case TargetOpcode::G_FSIN:

1783 case TargetOpcode::G_FTAN:

1784 case TargetOpcode::G_FACOS:

1785 case TargetOpcode::G_FASIN:

1786 case TargetOpcode::G_FATAN:

1787 case TargetOpcode::G_FATAN2:

1788 case TargetOpcode::G_FCOSH:

1789 case TargetOpcode::G_FSINH:

1790 case TargetOpcode::G_FTANH:

1791 case TargetOpcode::G_FSQRT:

1792 case TargetOpcode::G_FSUB:

1793 case TargetOpcode::G_INTRINSIC_ROUND:

1794 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:

1795 case TargetOpcode::G_INTRINSIC_TRUNC:

1796 return true;

1797 default:

1798 return false;

1799 }

1800}

1801

1802

1805 LLT Ty = MRI.getType(ShiftAmount);

1806

1807 if (Ty.isScalableVector())

1808 return false;

1809

1810 if (Ty.isScalar()) {

1811 std::optional Val =

1813 if (!Val)

1814 return false;

1815 return Val->Value.ult(Ty.getScalarSizeInBits());

1816 }

1817

1819 if (!BV)

1820 return false;

1821

1823 for (unsigned I = 0; I < Sources; ++I) {

1824 std::optional Val =

1826 if (!Val)

1827 return false;

1828 if (!Val->Value.ult(Ty.getScalarSizeInBits()))

1829 return false;

1830 }

1831

1832 return true;

1833}

1834

1835namespace {

1840};

1841}

1842

1846

1850

1852 bool ConsiderFlagsAndMetadata,

1855

1856 if (ConsiderFlagsAndMetadata && includesPoison(Kind))

1858 if (GMI->hasPoisonGeneratingFlags())

1859 return true;

1860

1861

1863 case TargetOpcode::G_BUILD_VECTOR:

1864 case TargetOpcode::G_CONSTANT_FOLD_BARRIER:

1865 return false;

1866 case TargetOpcode::G_SHL:

1867 case TargetOpcode::G_ASHR:

1868 case TargetOpcode::G_LSHR:

1871 case TargetOpcode::G_FPTOSI:

1872 case TargetOpcode::G_FPTOUI:

1873

1874

1875 return true;

1876 case TargetOpcode::G_CTLZ:

1877 case TargetOpcode::G_CTTZ:

1878 case TargetOpcode::G_ABS:

1879 case TargetOpcode::G_CTPOP:

1880 case TargetOpcode::G_BSWAP:

1881 case TargetOpcode::G_BITREVERSE:

1882 case TargetOpcode::G_FSHL:

1883 case TargetOpcode::G_FSHR:

1884 case TargetOpcode::G_SMAX:

1885 case TargetOpcode::G_SMIN:

1886 case TargetOpcode::G_SCMP:

1887 case TargetOpcode::G_UMAX:

1888 case TargetOpcode::G_UMIN:

1889 case TargetOpcode::G_UCMP:

1890 case TargetOpcode::G_PTRMASK:

1891 case TargetOpcode::G_SADDO:

1892 case TargetOpcode::G_SSUBO:

1893 case TargetOpcode::G_UADDO:

1894 case TargetOpcode::G_USUBO:

1895 case TargetOpcode::G_SMULO:

1896 case TargetOpcode::G_UMULO:

1897 case TargetOpcode::G_SADDSAT:

1898 case TargetOpcode::G_UADDSAT:

1899 case TargetOpcode::G_SSUBSAT:

1900 case TargetOpcode::G_USUBSAT:

1901 case TargetOpcode::G_SBFX:

1902 case TargetOpcode::G_UBFX:

1903 return false;

1904 case TargetOpcode::G_SSHLSAT:

1905 case TargetOpcode::G_USHLSAT:

1908 case TargetOpcode::G_INSERT_VECTOR_ELT: {

1911 std::optional Index =

1913 if (!Index)

1914 return true;

1915 LLT VecTy = MRI.getType(Insert->getVectorReg());

1917 }

1918 return false;

1919 }

1920 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {

1923 std::optional Index =

1925 if (!Index)

1926 return true;

1929 }

1930 return false;

1931 }

1932 case TargetOpcode::G_SHUFFLE_VECTOR: {

1936 }

1937 case TargetOpcode::G_FNEG:

1938 case TargetOpcode::G_PHI:

1939 case TargetOpcode::G_SELECT:

1940 case TargetOpcode::G_UREM:

1941 case TargetOpcode::G_SREM:

1942 case TargetOpcode::G_FREEZE:

1943 case TargetOpcode::G_ICMP:

1944 case TargetOpcode::G_FCMP:

1945 case TargetOpcode::G_FADD:

1946 case TargetOpcode::G_FSUB:

1947 case TargetOpcode::G_FMUL:

1948 case TargetOpcode::G_FDIV:

1949 case TargetOpcode::G_FREM:

1950 case TargetOpcode::G_PTR_ADD:

1951 return false;

1952 default:

1954 }

1955}

1956

1962 return false;

1963

1965

1967 case TargetOpcode::G_FREEZE:

1968 return true;

1969 case TargetOpcode::G_IMPLICIT_DEF:

1971 case TargetOpcode::G_CONSTANT:

1972 case TargetOpcode::G_FCONSTANT:

1973 return true;

1974 case TargetOpcode::G_BUILD_VECTOR: {

1977 for (unsigned I = 0; I < NumSources; ++I)

1979 Depth + 1, Kind))

1980 return false;

1981 return true;

1982 }

1983 case TargetOpcode::G_PHI: {

1985 unsigned NumIncoming = Phi->getNumIncomingValues();

1986 for (unsigned I = 0; I < NumIncoming; ++I)

1988 Depth + 1, Kind))

1989 return false;

1990 return true;

1991 }

1992 default: {

1994 if (!MO.isReg())

1995 return true;

1996 return ::isGuaranteedNotToBeUndefOrPoison(MO.getReg(), MRI, Depth + 1,

1997 Kind);

1998 };

2000 true, Kind) &&

2002 }

2003 }

2004}

2005

2007 bool ConsiderFlagsAndMetadata) {

2008 return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata,

2010}

2011

2013 bool ConsiderFlagsAndMetadata = true) {

2014 return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata,

2016}

2017

2020 unsigned Depth) {

2021 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,

2023}

2024

2027 unsigned Depth) {

2028 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,

2030}

2031

2034 unsigned Depth) {

2035 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,

2037}

2038

2040 if (Ty.isVector())

2042 Ty.getElementCount());

2044}

2045

2047 switch (MI.getOpcode()) {

2048 default:

2049 return false;

2050 case TargetOpcode::G_ASSERT_ALIGN:

2051 case TargetOpcode::G_ASSERT_SEXT:

2052 case TargetOpcode::G_ASSERT_ZEXT:

2053 return true;

2054 }

2055}

2056

2059

2060 return Value;

2061}

2062

2063std::optional

2066

2068 std::optional MayBeConstant =

2070 if (!MayBeConstant)

2071 return std::nullopt;

2073 }

2074

2077 unsigned NumSources = Build->getNumSources();

2078 for (unsigned I = 0; I < NumSources; ++I) {

2079 Register SrcReg = Build->getSourceReg(I);

2080 std::optional MayBeConstant =

2082 if (!MayBeConstant)

2083 return std::nullopt;

2084 Values.push_back(MayBeConstant->Value);

2085 }

2087 }

2088

2089 std::optional MayBeConstant =

2091 if (!MayBeConstant)

2092 return std::nullopt;

2093

2095}

2096

2099

2100 return Values[0];

2101}

2102

2103std::optional

2106

2108 std::optional MayBeConstant =

2110 if (!MayBeConstant)

2111 return std::nullopt;

2113 }

2114

2117 unsigned NumSources = Build->getNumSources();

2118 for (unsigned I = 0; I < NumSources; ++I) {

2119 Register SrcReg = Build->getSourceReg(I);

2120 std::optional MayBeConstant =

2122 if (!MayBeConstant)

2123 return std::nullopt;

2124 Values.push_back(MayBeConstant->Value);

2125 }

2127 }

2128

2129 std::optional MayBeConstant =

2131 if (!MayBeConstant)

2132 return std::nullopt;

2133

2135}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file declares a class to represent arbitrary precision floating point values and provide a varie...

This file implements a class to represent arbitrary precision integral constant values and operations...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Definition Utils.cpp:235

static bool includesPoison(UndefPoisonKind Kind)

Definition Utils.cpp:1843

static bool includesUndef(UndefPoisonKind Kind)

Definition Utils.cpp:1847

static bool shiftAmountKnownInRange(Register ShiftAmount, const MachineRegisterInfo &MRI)

Shifts return poison if shiftwidth is larger than the bitwidth.

Definition Utils.cpp:1803

static bool isBuildVectorOp(unsigned Opcode)

Definition Utils.cpp:1356

static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)

Definition Utils.cpp:1512

This file contains the declarations for the subclasses of Constant, which represent the different fla...

This contains common code to allow clients to notify changes to machine instr.

Provides analysis for querying information about KnownBits during GISel passes.

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

Tracks DebugLocs between checkpoints and verifies that they are transferred.

Contains matchers for matching SSA Machine Instructions.

This file declares the MachineIRBuilder class.

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

This file describes how to lower LLVM code to machine code.

Target-Independent Code Generator Pass Configuration Options pass.

static const char PassName[]

Class recording the (high level) value of a variable.

static constexpr roundingMode rmNearestTiesToEven

static const fltSemantics & IEEEhalf()

opStatus divide(const APFloat &RHS, roundingMode RM)

void copySign(const APFloat &RHS)

LLVM_ABI opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)

opStatus subtract(const APFloat &RHS, roundingMode RM)

opStatus add(const APFloat &RHS, roundingMode RM)

opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)

opStatus multiply(const APFloat &RHS, roundingMode RM)

APInt bitcastToAPInt() const

opStatus mod(const APFloat &RHS)

Class for arbitrary precision integers.

LLVM_ABI APInt udiv(const APInt &RHS) const

Unsigned division operation.

static APInt getAllOnes(unsigned numBits)

Return an APInt of a specified width with all bits set.

LLVM_ABI APInt zext(unsigned width) const

Zero extend to a new width.

LLVM_ABI APInt zextOrTrunc(unsigned width) const

Zero extend or truncate to width.

LLVM_ABI APInt trunc(unsigned width) const

Truncate to new width.

LLVM_ABI APInt urem(const APInt &RHS) const

Unsigned remainder operation.

unsigned getBitWidth() const

Return the number of bits in the APInt.

LLVM_ABI APInt sdiv(const APInt &RHS) const

Signed division function for APInt.

LLVM_ABI APInt sextOrTrunc(unsigned width) const

Sign extend or truncate to width.

APInt ashr(unsigned ShiftAmt) const

Arithmetic right-shift function.

LLVM_ABI APInt srem(const APInt &RHS) const

Function for signed remainder operation.

LLVM_ABI APInt sext(unsigned width) const

Sign extend to a new width.

bool isPowerOf2() const

Check if this APInt's value is a power of two greater than zero.

static bool isSameValue(const APInt &I1, const APInt &I2)

Determine if two APInts have the same value, after zero-extending one of them (if needed!...

static APInt getZero(unsigned numBits)

Get the '0' value for the specified bit-width.

static APInt getOneBitSet(unsigned numBits, unsigned BitNo)

Return an APInt with exactly one bit set in the result.

APInt lshr(unsigned shiftAmt) const

Logical right-shift function.

Represent the analysis usage information of a pass.

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

@ ICMP_SLT

signed less than

@ ICMP_SLE

signed less or equal

@ ICMP_UGE

unsigned greater or equal

@ ICMP_UGT

unsigned greater than

@ ICMP_SGT

signed greater than

@ ICMP_ULT

unsigned less than

@ ICMP_SGE

signed greater or equal

@ ICMP_ULE

unsigned less or equal

ConstantFP - Floating Point Values [float, double].

const APFloat & getValueAPF() const

bool isNegative() const

Return true if the sign bit is set.

bool isZero() const

Return true if the value is positive or negative zero.

This is the shared class of boolean and integer constants.

const APInt & getValue() const

Return the constant as an APInt value reference.

This is an important base class in LLVM.

static constexpr ElementCount getFixed(ScalarTy MinVal)

static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)

Represents a G_BUILD_VECTOR.

static LLVM_ABI std::optional< GFConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)

Definition Utils.cpp:2104

GFConstant(ArrayRef< APFloat > Values)

LLVM_ABI APFloat getScalarValue() const

Returns the value, if this constant is a scalar.

Definition Utils.cpp:2097

LLVM_ABI APInt getScalarValue() const

Returns the value, if this constant is a scalar.

Definition Utils.cpp:2057

static LLVM_ABI std::optional< GIConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)

Definition Utils.cpp:2064

GIConstant(ArrayRef< APInt > Values)

Abstract class that contains various methods for clients to notify about changes.

KnownBits getKnownBits(Register R)

void insert(MachineInstr *I)

Add the specified instruction to the worklist if it isn't already in it.

MachineInstr * pop_back_val()

void remove(const MachineInstr *I)

Remove I from the worklist if it exists.

Represents an insert vector element.

Returns the I'th source register.

unsigned getNumSources() const

Returns the number of source registers.

Represents a G_SHUFFLE_VECTOR.

ArrayRef< int > getMask() const

Represents a splat vector.

Module * getParent()

Get the module that this global value is contained inside of...

static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

constexpr bool isScalableVector() const

Returns true if the LLT is a scalable vector.

constexpr unsigned getScalarSizeInBits() const

static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)

Get a low-level vector of some number of elements and element width.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isValid() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

constexpr bool isScalable() const

Returns true if the LLT is a scalable vector.

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr LLT getElementType() const

Returns the vector's element type. Only valid for vector types.

constexpr ElementCount getElementCount() const

static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)

Get a low-level fixed-width vector of some number of elements and element width.

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

constexpr LLT getScalarType() const

static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)

This is an important class for using LLVM in a threaded context.

void checkpoint(bool CheckDebugLocs=true)

Call this to indicate that it's a good point to assess whether locations have been lost.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

MachineInstrBundleIterator< MachineInstr > iterator

LLVM_ABI bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const

Return true if the specified register is in the live in set.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

GISelChangeObserver * getObserver() const

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

const MachineBasicBlock & front() const

addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Helper class to build MachineInstr.

MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)

Build and insert Res0, ... = G_UNMERGE_VALUES Op.

MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)

Build and insert Res0, ... = G_EXTRACT Src, Idx0.

MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...

Get the register for the operand index.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

mop_range uses()

Returns all operands which may be register uses.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

const ConstantInt * getCImm() const

bool isCImm() const

isCImm - Test if this is a MO_CImmediate operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

const ConstantFP * getFPImm() const

bool isFPImm() const

isFPImm - Tests if this is a MO_FPImmediate operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Represents a value which can be a Register or a constant.

Holds all the information related to register banks.

static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)

Constrain the (possibly generic) virtual register Reg to RC.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

BooleanContent getBooleanContents(bool isVec, bool isFloat) const

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...

@ ZeroOrOneBooleanContent

@ UndefinedBooleanContent

@ ZeroOrNegativeOneBooleanContent

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

GlobalISelAbortMode GlobalISelAbort

EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

static LLVM_ABI VectorType * get(Type *ElementType, ElementCount EC)

This static method is the primary way to construct an VectorType.

constexpr ScalarTy getFixedValue() const

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

constexpr LeafTy multiplyCoefficientBy(ScalarTy RHS) const

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

const APInt & smin(const APInt &A, const APInt &B)

Determine the smaller of two APInts considered to be signed.

const APInt & smax(const APInt &A, const APInt &B)

Determine the larger of two APInts considered to be signed.

const APInt & umin(const APInt &A, const APInt &B)

Determine the smaller of two APInts considered to be unsigned.

const APInt & umax(const APInt &A, const APInt &B)

Determine the larger of two APInts considered to be unsigned.

@ C

The default llvm calling convention, compatible with C.

DiagnosticInfoMIROptimization::MachineArgument MNV

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())

Return a virtual register corresponding to the incoming argument register PhysReg.

Definition Utils.cpp:920

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

LLVM_ABI std::optional< SmallVector< APInt > > ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2, unsigned DstScalarSizeInBits, unsigned ExtOp, const MachineRegisterInfo &MRI)

Definition Utils.cpp:1039

LLVM_ABI bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...

Definition Utils.cpp:1486

LLVM_ABI Type * getTypeForLLT(LLT Ty, LLVMContext &C)

Get the type back from LLT.

Definition Utils.cpp:2039

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)

Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...

Definition Utils.cpp:56

LLVM_ABI MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)

See if Reg is defined by an single def instruction that is Opcode.

Definition Utils.cpp:652

LLVM_ABI const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)

Definition Utils.cpp:460

LLVM_ABI bool canCreatePoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT, return the corresponding value.

Definition Utils.cpp:295

LLVM_ABI std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)

Definition Utils.cpp:994

LLVM_ABI std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)

Definition Utils.cpp:1446

LLVM_ABI bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)

Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...

Definition Utils.cpp:1611

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)

Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.

LLVM_ABI std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

Definition Utils.cpp:740

LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)

Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...

Definition Utils.cpp:1729

LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)

Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...

Definition Utils.cpp:155

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

auto dyn_cast_if_present(const Y &Val)

dyn_cast_if_present - Functionally identical to dyn_cast, except that a null (or none in the case ...

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

LLVM_ABI std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)

Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.

Definition Utils.cpp:1007

LLVM_ABI std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)

Definition Utils.cpp:953

LLVM_ABI std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Definition Utils.cpp:1499

LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)

Implements IEEE 754-2019 maximum semantics.

GISelWorkList< 4 > SmallInstListTy

LLVM_ABI std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)

Determines if MI defines a constant integer or a splat vector of constant integers.

Definition Utils.cpp:1569

LLVM_ABI bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)

Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...

Definition Utils.cpp:1593

LLVM_ABI MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the def instruction for Reg, folding away any trivial copies.

Definition Utils.cpp:493

LLVM_ABI bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)

Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...

Definition Utils.cpp:1626

bool isPreISelGenericOptimizationHint(unsigned Opcode)

LLVM_ABI void reportGISelWarning(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.

Definition Utils.cpp:253

LLVM_ABI bool isGuaranteedNotToBeUndef(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Returns true if V cannot be undef, but may be poison.

LLVM_ABI bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)

Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...

Definition Utils.cpp:1658

LLVM_ABI LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)

Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...

Definition Utils.cpp:1193

LLVM_ABI std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT fits in int64_t returns it.

Definition Utils.cpp:315

LLVM_ABI std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

Definition Utils.cpp:671

auto dyn_cast_or_null(const Y &Val)

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI const APInt & getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI)

VReg is defined by a G_CONSTANT, return the corresponding value.

Definition Utils.cpp:306

LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)

Implements IEEE-754 2008 maxNum semantics.

LLVM_ABI bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)

Return true if the specified instruction is known to be a constant, or a vector of constants.

Definition Utils.cpp:1549

constexpr unsigned MaxAnalysisRecursionDepth

auto reverse(ContainerTy &&C)

LLVM_ABI bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)

Check if DstReg can be replaced with SrcReg depending on the register constraints.

Definition Utils.cpp:201

LLVM_ABI void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)

Definition Utils.cpp:1695

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.

Definition Utils.cpp:259

LLVM_ABI std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...

Definition Utils.cpp:440

LLVM_ABI bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...

Definition Utils.cpp:1492

LLVM_ABI bool canCreateUndefOrPoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)

canCreateUndefOrPoison returns true if Op can create undef or poison from non-undef & non-poison oper...

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

LLVM_ABI SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

Tries to constant fold a vector binop with sources Op1 and Op2.

Definition Utils.cpp:798

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)

Returns a floating point scalar constant of a build vector splat if it exists.

Definition Utils.cpp:1479

LLVM_ABI std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)

Definition Utils.cpp:970

LLVM_ABI void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)

Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...

Definition Utils.cpp:507

LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)

Modify analysis usage so it preserves passes required for the SelectionDAG fallback.

Definition Utils.cpp:1189

LLVM_ABI LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)

Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.

Definition Utils.cpp:1260

LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)

Implements IEEE-754 2008 minNum semantics.

LLVM_ABI unsigned getInverseGMinMaxOpcode(unsigned MinMaxOpc)

Returns the inverse opcode of MinMaxOpc, which is a generic min/max opcode like G_SMIN.

Definition Utils.cpp:280

@ Mul

Product of integers.

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

bool isTargetSpecificOpcode(unsigned Opcode)

Check whether the given Opcode is a target-specific opcode.

DWARFExpression::Operation Op

LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Return true if this function can prove that V does not have undef bits and is never poison.

LLVM_ABI std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...

Definition Utils.cpp:448

LLVM_ABI bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)

Definition Utils.cpp:1671

LLVM_ABI std::optional< APFloat > isConstantOrConstantSplatVectorFP(MachineInstr &MI, const MachineRegisterInfo &MRI)

Determines if MI defines a float constant integer or a splat vector of float constant integers.

Definition Utils.cpp:1582

constexpr unsigned BitWidth

LLVM_ABI APFloat getAPFloatFromSize(double Val, unsigned Size)

Returns an APFloat from Val converted to the appropriate size.

Definition Utils.cpp:658

LLVM_ABI bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)

Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...

Definition Utils.cpp:1405

LLVM_ABI void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)

Definition Utils.cpp:1724

DiagnosticSeverity

Defines the different supported severity of a diagnostic.

LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)

Try to constrain Reg to the specified register class.

Definition Utils.cpp:46

LLVM_ABI int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)

Returns an integer representing true, as defined by the TargetBooleanContents.

Definition Utils.cpp:1683

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isKnownNeverNaN(const Value *V, const SimplifyQuery &SQ, unsigned Depth=0)

Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...

LLVM_ABI std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...

Definition Utils.cpp:434

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...

Definition Utils.cpp:1748

bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)

Returns true if Val can be assumed to never be a signaling NaN.

LLVM_ABI std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the def instruction for Reg, and underlying value Register folding away any copies.

Definition Utils.cpp:468

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

LLVM_ABI void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)

Definition Utils.cpp:1709

void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)

Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...

LLVM_ABI bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)

Return true if the given value is known to have exactly one bit set when defined.

LLVM_ABI Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the source register for Reg, folding away any trivial copies.

Definition Utils.cpp:500

LLVM_ABI LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)

Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.

Definition Utils.cpp:1281

LLVM_ABI bool isGuaranteedNotToBePoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Returns true if V cannot be poison, but may be undef.

LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)

Implements IEEE 754-2019 minimum semantics.

LLVM_ABI std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)

Definition Utils.cpp:1464

LLVM_ABI bool isAssertMI(const MachineInstr &MI)

Returns true if the instruction MI is one of the assert instructions.

Definition Utils.cpp:2046

LLVM_ABI void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)

Version which handles irregular sub-vector splits.

Definition Utils.cpp:610

LLVM_ABI int getSplatIndex(ArrayRef< int > Mask)

If all non-negative Mask elements are the same value, return that value.

LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...

Definition Utils.cpp:222

LLVM_ABI Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)

Definition Utils.cpp:903

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Simple struct used to hold a Register value and the instruction which defines it.

unsigned countMaxPopulation() const

Returns the maximum number of bits that could be one.

unsigned countMinPopulation() const

Returns the number of bits known to be one.

This class contains a discriminated union of information about pointers in memory operands,...

int64_t Offset

Offset - This is an offset from the base Value*.

PointerUnion< const Value *, const PseudoSourceValue * > V

This is the IR pointer value for the access, or it is null if unknown.

Simple struct used to hold a constant integer value and a virtual register.