LLVM: lib/Target/Hexagon/HexagonBitTracker.cpp Source File (original) (raw)
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49
50
51 unsigned InVirtReg, InPhysReg = 0;
52
53 for (const Argument &Arg : MF.getFunction().args()) {
54 Type *ATy = Arg.getType();
55 unsigned Width = 0;
56 if (ATy->isIntegerTy())
57 Width = ATy->getIntegerBitWidth();
58 else if (ATy->isPointerTy())
59 Width = 32;
60
61
62 if (Width == 0 || Width > 64)
63 break;
64 if (Arg.hasAttribute(Attribute::ByVal))
65 continue;
66 InPhysReg = getNextPhysReg(InPhysReg, Width);
67 if (!InPhysReg)
68 break;
69 InVirtReg = getVirtRegFor(InPhysReg);
70 if (!InVirtReg)
71 continue;
72 if (Arg.hasAttribute(Attribute::SExt))
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
74 else if (Arg.hasAttribute(Attribute::ZExt))
75 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
76 }
77}
80 if (Sub == 0)
81 return MachineEvaluator::mask(Reg, 0);
87 switch (ID) {
88 case Hexagon::DoubleRegsRegClassID:
89 case Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID:
90 case Hexagon::HvxWRRegClassID:
91 case Hexagon::HvxVQRRegClassID:
94 default:
95 break;
96 }
97#ifndef NDEBUG
99 << TRI.getRegClassName(&RC) << '\n';
100#endif
102}
107 if (HST.useHVXOps()) {
108 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
109 HvxVQRRegClass})
110 if (RC.contains(Reg))
111 return TRI.getRegSizeInBits(RC);
112 }
113
115 return TRI.getRegSizeInBits(*RC);
116
118 (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
119}
123 if (Idx == 0)
124 return RC;
125
126#ifndef NDEBUG
128 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
129 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
130 assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
131#endif
132
133 switch (RC.getID()) {
134 case Hexagon::DoubleRegsRegClassID:
135 case Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID:
136 return Hexagon::IntRegsRegClass;
137 case Hexagon::HvxWRRegClassID:
138 return Hexagon::HvxVRRegClass;
139 case Hexagon::HvxVQRRegClassID:
140 return Hexagon::HvxWRRegClass;
141 default:
142 break;
143 }
144#ifndef NDEBUG
145 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
146#endif
147 llvm_unreachable("Unimplemented combination of reg class/subreg idx");
148}
181
182 unsigned NumDefs = 0;
183
184
186 if (!MO.isReg() || !MO.isDef())
187 continue;
188 NumDefs++;
189 assert(MO.getSubReg() == 0);
190 }
191
192 if (NumDefs == 0)
193 return false;
194
195 unsigned Opc = MI.getOpcode();
196
197 if (MI.mayLoad()) {
198 switch (Opc) {
199
200
201 case CONST32:
202 case CONST64:
203 break;
204 default:
205 return evaluateLoad(MI, Inputs, Outputs);
206 }
207 }
208
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221
222
223 if (MI.isCopy()) {
224 if (evaluateFormalCopy(MI, Inputs, Outputs))
225 return true;
226 }
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229
230
231
232
233
235 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
236 MO.isCPI())
237 return false;
238 }
239
241#define op(i) MI.getOperand(i)
242#define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
243#define im(i) MI.getOperand(i).getImm()
244
245
246 if (Reg.size() == 0)
247 return false;
248
249
251 -> bool {
252 putCell(Reg[0], Val, Outputs);
253 return true;
254 };
255
256 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
259 if (Op.isImm())
260 return eIMM(Op.getImm(), W);
261 if (.isReg())
265 };
266
270 return eXTR(RC, 0, RW);
271 };
272
277 return eXTR(RC, W-RW, W);
278 };
279
283 return eXTR(RC, N*16, N*16+16);
284 };
285
291 I += 2;
292 while (I*BW < Ws) {
294 I += 2;
295 }
296 return RC;
297 };
298
299
300
301
302
304
305
306 unsigned Reg0 = Reg[0].Reg;
307
308 switch (Opc) {
309
310
311 case A2_tfrsi:
312 case A2_tfrpi:
313 case CONST32:
314 case CONST64:
315 return rr0(eIMM(im(1), W0), Outputs);
316 case PS_false:
317 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
318 case PS_true:
319 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
320 case PS_fi: {
321 int FI = op(1).getIndex();
322 int Off = op(2).getImm();
323 unsigned A = MFI.getObjectAlign(FI).value() + std::abs(Off);
326 RC.fill(0, L, BT::BitValue::Zero);
327 return rr0(RC, Outputs);
328 }
329
330
331
332 case A2_tfr:
333 case A2_tfrp:
334 case C2_pxfer_map:
335 return rr0(rc(1), Outputs);
336 case C2_tfrpr: {
338 uint16_t PW = 8;
342 RC.fill(PW, RW, BT::BitValue::Zero);
343 return rr0(RC, Outputs);
344 }
345 case C2_tfrrp: {
347 uint16_t PW = 8;
349 RC.fill(PW, RW, BT::BitValue::Zero);
350 return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
351 }
352
353
354
355 case A2_abs:
356 case A2_absp:
357
358 break;
359
360 case A2_addsp: {
362 assert(W0 == 64 && W1 == 32);
365 return rr0(RC, Outputs);
366 }
367 case A2_add:
368 case A2_addp:
369 return rr0(eADD(rc(1), rc(2)), Outputs);
370 case A2_addi:
371 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
372 case S4_addi_asl_ri: {
374 return rr0(RC, Outputs);
375 }
376 case S4_addi_lsr_ri: {
378 return rr0(RC, Outputs);
379 }
380 case S4_addaddi: {
382 return rr0(RC, Outputs);
383 }
384 case M4_mpyri_addi: {
387 return rr0(RC, Outputs);
388 }
389 case M4_mpyrr_addi: {
392 return rr0(RC, Outputs);
393 }
394 case M4_mpyri_addr_u2: {
397 return rr0(RC, Outputs);
398 }
399 case M4_mpyri_addr: {
402 return rr0(RC, Outputs);
403 }
404 case M4_mpyrr_addr: {
407 return rr0(RC, Outputs);
408 }
409 case S4_subaddi: {
411 return rr0(RC, Outputs);
412 }
413 case M2_accii: {
415 return rr0(RC, Outputs);
416 }
417 case M2_acci: {
419 return rr0(RC, Outputs);
420 }
421 case M2_subacc: {
423 return rr0(RC, Outputs);
424 }
425 case S2_addasl_rrri: {
427 return rr0(RC, Outputs);
428 }
429 case C4_addipc: {
431 RPC.fill(0, 2, BT::BitValue::Zero);
432 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
433 }
434 case A2_sub:
435 case A2_subp:
436 return rr0(eSUB(rc(1), rc(2)), Outputs);
437 case A2_subri:
438 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
439 case S4_subi_asl_ri: {
441 return rr0(RC, Outputs);
442 }
443 case S4_subi_lsr_ri: {
445 return rr0(RC, Outputs);
446 }
447 case M2_naccii: {
449 return rr0(RC, Outputs);
450 }
451 case M2_nacci: {
453 return rr0(RC, Outputs);
454 }
455
456 case A2_negp:
457 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
458
459 case M2_mpy_up: {
461 return rr0(hi(M, W0), Outputs);
462 }
463 case M2_dpmpyss_s0:
464 return rr0(eMLS(rc(1), rc(2)), Outputs);
465 case M2_dpmpyss_acc_s0:
466 return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
467 case M2_dpmpyss_nac_s0:
468 return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
469 case M2_mpyi: {
471 return rr0(lo(M, W0), Outputs);
472 }
473 case M2_macsip: {
476 return rr0(RC, Outputs);
477 }
478 case M2_macsin: {
481 return rr0(RC, Outputs);
482 }
483 case M2_maci: {
486 return rr0(RC, Outputs);
487 }
488 case M2_mnaci: {
491 return rr0(RC, Outputs);
492 }
493 case M2_mpysmi: {
495 return rr0(lo(M, 32), Outputs);
496 }
497 case M2_mpysin: {
499 return rr0(lo(M, 32), Outputs);
500 }
501 case M2_mpysip: {
503 return rr0(lo(M, 32), Outputs);
504 }
505 case M2_mpyu_up: {
507 return rr0(hi(M, W0), Outputs);
508 }
509 case M2_dpmpyuu_s0:
510 return rr0(eMLU(rc(1), rc(2)), Outputs);
511 case M2_dpmpyuu_acc_s0:
512 return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
513 case M2_dpmpyuu_nac_s0:
514 return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
515
516
517
518
519 case A2_andir:
520 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
521 case A2_and:
522 case A2_andp:
523 return rr0(eAND(rc(1), rc(2)), Outputs);
524 case A4_andn:
525 case A4_andnp:
526 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
527 case S4_andi_asl_ri: {
529 return rr0(RC, Outputs);
530 }
531 case S4_andi_lsr_ri: {
533 return rr0(RC, Outputs);
534 }
535 case M4_and_and:
536 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
537 case M4_and_andn:
539 case M4_and_or:
540 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
541 case M4_and_xor:
542 return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
543 case A2_orir:
544 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
545 case A2_or:
546 case A2_orp:
547 return rr0(eORL(rc(1), rc(2)), Outputs);
548 case A4_orn:
549 case A4_ornp:
550 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
551 case S4_ori_asl_ri: {
553 return rr0(RC, Outputs);
554 }
555 case S4_ori_lsr_ri: {
557 return rr0(RC, Outputs);
558 }
559 case M4_or_and:
560 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
561 case M4_or_andn:
563 case S4_or_andi:
564 case S4_or_andix: {
566 return rr0(RC, Outputs);
567 }
568 case S4_or_ori: {
570 return rr0(RC, Outputs);
571 }
572 case M4_or_or:
573 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
574 case M4_or_xor:
575 return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
576 case A2_xor:
577 case A2_xorp:
578 return rr0(eXOR(rc(1), rc(2)), Outputs);
579 case M4_xor_and:
580 return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
581 case M4_xor_andn:
583 case M4_xor_or:
584 return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
585 case M4_xor_xacc:
586 return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
587 case A2_not:
588 case A2_notp:
589 return rr0(eNOT(rc(1)), Outputs);
590
591 case S2_asl_i_r:
592 case S2_asl_i_p:
593 return rr0(eASL(rc(1), im(2)), Outputs);
594 case A2_aslh:
595 return rr0(eASL(rc(1), 16), Outputs);
596 case S2_asl_i_r_acc:
597 case S2_asl_i_p_acc:
598 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
599 case S2_asl_i_r_nac:
600 case S2_asl_i_p_nac:
601 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
602 case S2_asl_i_r_and:
603 case S2_asl_i_p_and:
604 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
605 case S2_asl_i_r_or:
606 case S2_asl_i_p_or:
607 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
608 case S2_asl_i_r_xacc:
609 case S2_asl_i_p_xacc:
610 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
611 case S2_asl_i_vh:
612 case S2_asl_i_vw:
613
614 break;
615
616 case S2_asr_i_r:
617 case S2_asr_i_p:
618 return rr0(eASR(rc(1), im(2)), Outputs);
619 case A2_asrh:
620 return rr0(eASR(rc(1), 16), Outputs);
621 case S2_asr_i_r_acc:
622 case S2_asr_i_p_acc:
623 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
624 case S2_asr_i_r_nac:
625 case S2_asr_i_p_nac:
626 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
627 case S2_asr_i_r_and:
628 case S2_asr_i_p_and:
629 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
630 case S2_asr_i_r_or:
631 case S2_asr_i_p_or:
632 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
633 case S2_asr_i_r_rnd: {
634
635
639 return rr0(eXTR(RC, 0, W0), Outputs);
640 }
641 case S2_asr_i_r_rnd_goodsyntax: {
642 int64_t S = im(2);
643 if (S == 0)
644 return rr0(rc(1), Outputs);
645
648 return rr0(eXTR(RC, 0, W0), Outputs);
649 }
650 case S2_asr_r_vh:
651 case S2_asr_i_vw:
652 case S2_asr_i_svw_trun:
653
654 break;
655
656 case S2_lsr_i_r:
657 case S2_lsr_i_p:
658 return rr0(eLSR(rc(1), im(2)), Outputs);
659 case S2_lsr_i_r_acc:
660 case S2_lsr_i_p_acc:
661 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
662 case S2_lsr_i_r_nac:
663 case S2_lsr_i_p_nac:
664 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
665 case S2_lsr_i_r_and:
666 case S2_lsr_i_p_and:
667 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
668 case S2_lsr_i_r_or:
669 case S2_lsr_i_p_or:
670 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
671 case S2_lsr_i_r_xacc:
672 case S2_lsr_i_p_xacc:
673 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
674
675 case S2_clrbit_i: {
677 RC[im(2)] = BT::BitValue::Zero;
678 return rr0(RC, Outputs);
679 }
680 case S2_setbit_i: {
682 RC[im(2)] = BT::BitValue::One;
683 return rr0(RC, Outputs);
684 }
685 case S2_togglebit_i: {
688 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
689 : RC[BX].is(1) ? BT::BitValue::Zero
690 : BT::BitValue::self();
691 return rr0(RC, Outputs);
692 }
693
694 case A4_bitspliti: {
697
698 const BT::BitValue Zero = BT::BitValue::Zero;
700 .fill(W1+(W1-BX), W0, Zero);
703 return rr0(RC, Outputs);
704 }
705 case S4_extract:
706 case S4_extractp:
707 case S2_extractu:
708 case S2_extractup: {
711 if (Wd == 0)
712 return rr0(eIMM(0, W0), Outputs);
713
714
717
719 if (Opc == S2_extractu || Opc == S2_extractup)
720 return rr0(eZXT(RC, Wd), Outputs);
721 return rr0(eSXT(RC, Wd), Outputs);
722 }
723 case S2_insert:
724 case S2_insertp: {
726 assert(Wd < W0 && Of < W0);
727
728 if (Wd+Of > W0)
729 Wd = W0-Of;
730 if (Wd == 0)
731 return rr0(rc(1), Outputs);
732 return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
733 }
734
735
736
737 case A2_combineii:
738 case A4_combineii:
739 case A4_combineir:
740 case A4_combineri:
741 case A2_combinew:
742 case V6_vcombine:
744 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
745 case A2_combine_ll:
746 case A2_combine_lh:
747 case A2_combine_hl:
748 case A2_combine_hh: {
751
752 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
753
754 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
758 return rr0(RC, Outputs);
759 }
760 case S2_packhl: {
766 .cat(half(R1, 1));
767 return rr0(RC, Outputs);
768 }
769 case S2_shuffeb: {
771 return rr0(RC, Outputs);
772 }
773 case S2_shuffeh: {
775 return rr0(RC, Outputs);
776 }
777 case S2_shuffob: {
779 return rr0(RC, Outputs);
780 }
781 case S2_shuffoh: {
783 return rr0(RC, Outputs);
784 }
785 case C2_mask: {
787 uint16_t WP = 8;
788 assert(WR == 64 && WP == 8);
791 for (uint16_t i = 0; i < WP; ++i) {
793 BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
795 }
796 return rr0(RC, Outputs);
797 }
798
799
800
801 case C2_muxii:
802 case C2_muxir:
803 case C2_muxri:
804 case C2_mux: {
808 if (PC0.is(0) || PC0.is(1))
810 R2.meet(R3, Reg[0].Reg);
811 return rr0(R2, Outputs);
812 }
813 case C2_vmux:
814
815 break;
816
817
818
819 case A2_sxtb:
820 return rr0(eSXT(rc(1), 8), Outputs);
821 case A2_sxth:
822 return rr0(eSXT(rc(1), 16), Outputs);
823 case A2_sxtw: {
825 assert(W0 == 64 && W1 == 32);
827 return rr0(RC, Outputs);
828 }
829 case A2_zxtb:
830 return rr0(eZXT(rc(1), 8), Outputs);
831 case A2_zxth:
832 return rr0(eZXT(rc(1), 16), Outputs);
833
834
835
836 case A2_satb:
838 case A2_sath:
840 case A2_satub:
842 case A2_satuh:
844
845
846
847 case S2_cl0:
848 case S2_cl0p:
849
850 return rr0(eCLB(rc(1), false, 32), Outputs);
851 case S2_cl1:
852 case S2_cl1p:
853 return rr0(eCLB(rc(1), true, 32), Outputs);
854 case S2_clb:
855 case S2_clbp: {
860 return rr0(eCLB(R1, TV, 32), Outputs);
861 break;
862 }
863 case S2_ct0:
864 case S2_ct0p:
865 return rr0(eCTB(rc(1), false, 32), Outputs);
866 case S2_ct1:
867 case S2_ct1p:
868 return rr0(eCTB(rc(1), true, 32), Outputs);
869 case S5_popcountp:
870
871 break;
872
873 case C2_all8: {
875 bool Has0 = false, All1 = true;
876 for (uint16_t i = 0; i < 8; ++i) {
877 if (!P1[i].is(1))
878 All1 = false;
879 if (!P1[i].is(0))
880 continue;
881 Has0 = true;
882 break;
883 }
884 if (!Has0 && !All1)
885 break;
887 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
888 return rr0(RC, Outputs);
889 }
890 case C2_any8: {
892 bool Has1 = false, All0 = true;
893 for (uint16_t i = 0; i < 8; ++i) {
894 if (!P1[i].is(0))
895 All0 = false;
896 if (!P1[i].is(1))
897 continue;
898 Has1 = true;
899 break;
900 }
901 if (!Has1 && !All0)
902 break;
904 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
905 return rr0(RC, Outputs);
906 }
907 case C2_and:
908 return rr0(eAND(rc(1), rc(2)), Outputs);
909 case C2_andn:
910 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
911 case C2_not:
912 return rr0(eNOT(rc(1)), Outputs);
913 case C2_or:
914 return rr0(eORL(rc(1), rc(2)), Outputs);
915 case C2_orn:
916 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
917 case C2_xor:
918 return rr0(eXOR(rc(1), rc(2)), Outputs);
919 case C4_and_and:
920 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
921 case C4_and_andn:
923 case C4_and_or:
924 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
925 case C4_and_orn:
927 case C4_or_and:
928 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
929 case C4_or_andn:
931 case C4_or_or:
932 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
933 case C4_or_orn:
935 case C2_bitsclr:
936 case C2_bitsclri:
937 case C2_bitsset:
938 case C4_nbitsclr:
939 case C4_nbitsclri:
940 case C4_nbitsset:
941
942 break;
943 case S2_tstbit_i:
944 case S4_ntstbit_i: {
946 if (V.is(0) || V.is(1)) {
947
948 bool TV = (Opc == S2_tstbit_i);
949 BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
951 }
952 break;
953 }
954
955 default:
956
957
958 if (unsigned DefR = getUniqueDefVReg(MI)) {
959 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
962 uint16_t PW = 8;
964 RC.fill(PW, RW, BT::BitValue::Zero);
965 putCell(PD, RC, Outputs);
966 return true;
967 }
968 }
969 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
970 }
971 #undef im
972 #undef rc
973 #undef op
974 return false;
975}
980 bool &FallsThru) const {
981
982
984 bool SimpleBranch = false;
985 bool Negated = false;
986 switch (Opc) {
987 case Hexagon::J2_jumpf:
988 case Hexagon::J2_jumpfpt:
989 case Hexagon::J2_jumpfnew:
990 case Hexagon::J2_jumpfnewpt:
991 Negated = true;
992 [[fallthrough]];
993 case Hexagon::J2_jumpt:
994 case Hexagon::J2_jumptpt:
995 case Hexagon::J2_jumptnew:
996 case Hexagon::J2_jumptnewpt:
997
998
999 SimpleBranch = true;
1000 break;
1001 case Hexagon::J2_jump:
1003 FallsThru = false;
1004 return true;
1005 default:
1006
1007
1008 return false;
1009 }
1010
1011 if (!SimpleBranch)
1012 return false;
1013
1014
1018
1019
1020 if (.is(0) &&
.is(1))
1021 return false;
1022
1023
1024 if (.is(!Negated)) {
1025
1026 FallsThru = true;
1027 return true;
1028 }
1029
1031 FallsThru = false;
1032 return true;
1033}
1242unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {