LLVM: llvm::TargetRegisterClass Class Reference (original) (raw)

#include "[llvm/CodeGen/TargetRegisterInfo.h](TargetRegisterInfo%5F8h%5Fsource.html)"

Public Member Functions
unsigned getID () const
Return the register class ID number.
iterator begin () const
begin/end - Return all of the registers in this class.
iterator end () const
unsigned getNumRegs () const
Return the number of registers in this class.
ArrayRef< MCPhysReg > getRegisters () const
MCRegister getRegister (unsigned i) const
Return the specified register in the class.
bool contains (Register Reg) const
Return true if the specified register is included in this register class.
bool contains (Register Reg1, Register Reg2) const
Return true if both registers are in this class.
int getCopyCost () const
Return the cost of copying a value between two registers in this class.
bool isAllocatable () const
Return true if this register class may be used to create virtual registers.
bool isBaseClass () const
Return true if this register class has a defined BaseClassOrder.
bool hasSubClass (const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
bool hasSubClassEq (const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSuperClass (const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool hasSuperClassEq (const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const uint32_t * getSubClassMask () const
Returns a bit vector of subclasses, including this one.
const uint16_t * getSuperRegIndices () const
Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.
ArrayRef< unsigned > superclasses () const
Returns a list of super-classes.
bool isASubClass () const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
ArrayRef< MCPhysReg > getRawAllocationOrder (const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
LaneBitmask getLaneMask () const
Returns the combination of all lane masks of register in this class.
Public Attributes
const MCRegisterClass * MC
const uint32_t * SubClassMask
const uint16_t * SuperRegIndices
const LaneBitmask LaneMask
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.
const bool GlobalPriority
const uint8_t TSFlags
Configurable target specific flags.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
const unsigned * SuperClasses
const uint16_t SuperClassesSize
ArrayRef< MCPhysReg >(* OrderFunc )(const MachineFunction &)

Definition at line 44 of file TargetRegisterInfo.h.

◆ const_iterator

◆ iterator

◆ begin()

iterator llvm::TargetRegisterClass::begin ( ) const inline

◆ contains() [1/2]

bool llvm::TargetRegisterClass::contains ( Register Reg) const inline

Return true if the specified register is included in this register class.

This does not include virtual registers.

FIXME: Historically this function has returned false when given vregs but it should probably only receive physical registers

Definition at line 94 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::contains(), MC, and Reg.

Referenced by addHints(), llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::PPCInstrInfo::ClobbersPredicate(), llvm::VirtRegAuxInfo::copyHint(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), estimateRSStackSizeLimit(), llvm::SIInstrInfo::foldImmediate(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMatchingMegaReg(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::rewriteT2FrameIndex(), llvm::SystemZRegisterInfo::shouldCoalesce(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ contains() [2/2]

◆ end()

iterator llvm::TargetRegisterClass::end ( ) const inline

◆ getCopyCost()

int llvm::TargetRegisterClass::getCopyCost ( ) const inline

◆ getID()

unsigned llvm::TargetRegisterClass::getID ( ) const inline

Return the register class ID number.

Definition at line 73 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getID(), and MC.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::HexagonEvaluator::composeWithSubRegIndex(), llvm::RegisterBank::covers(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::SITargetLowering::finalizeLowering(), llvm::HexagonRegisterInfo::getCallerSavedRegs(), llvm::WebAssembly::getCopyOpcodeForRegClass(), GetCostForDef(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::PPCRegisterBankInfo::getRegBankFromRegClass(), llvm::SPIRVRegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPU::getRegBitWidth(), llvm::TargetRegisterInfo::getRegClassInfo(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::X86RegisterInfo::isTileRegisterClass(), IsWritingToVCCR(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::HexagonEvaluator::mask(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AArch64RegisterInfo::shouldCoalesce(), and llvm::HexagonRegisterInfo::shouldCoalesce().

◆ getLaneMask()

LaneBitmask llvm::TargetRegisterClass::getLaneMask ( ) const inline

◆ getNumRegs()

unsigned llvm::TargetRegisterClass::getNumRegs ( ) const inline

◆ getRawAllocationOrder()

Returns the preferred order for allocating registers from this register class in MF.

The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.

The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.

By default, this method returns all registers in the class.

Definition at line 201 of file TargetRegisterInfo.h.

References getRegisters(), and OrderFunc.

Referenced by getAllocatableSetForRC(), and llvm::RegScavenger::scavengeRegisterBackwards().

◆ getRegister()

◆ getRegisters()

◆ getSubClassMask()

const uint32_t * llvm::TargetRegisterClass::getSubClassMask ( ) const inline

Returns a bit vector of subclasses, including this one.

The vector is indexed by class IDs.

To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.

See the implementation of hasSubClassEq for an example of how it can be used.

Definition at line 162 of file TargetRegisterInfo.h.

References SubClassMask.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass().

◆ getSuperRegIndices()

const uint16_t * llvm::TargetRegisterClass::getSuperRegIndices ( ) const inline

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.

The list has an entry for each Idx such that:

There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Definition at line 173 of file TargetRegisterInfo.h.

References SuperRegIndices.

◆ hasSubClass()

◆ hasSubClassEq()

◆ hasSuperClass()

◆ hasSuperClassEq()

Returns true if RC is a super-class of or equal to this class.

Definition at line 142 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::SIInstrInfo::foldMemoryOperandImpl(), isFRClass(), isGRClass(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIRegisterInfo::isProperlyAlignedRC(), isVKClass(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SystemZRegisterInfo::shouldCoalesce(), and llvm::X86RegisterInfo::shouldRewriteCopySrc().

◆ isAllocatable()

bool llvm::TargetRegisterClass::isAllocatable ( ) const inline

◆ isASubClass()

bool llvm::TargetRegisterClass::isASubClass ( ) const inline

◆ isBaseClass()

bool llvm::TargetRegisterClass::isBaseClass ( ) const inline

◆ superclasses()

◆ AllocationPriority

Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.

The value is in the range [0,31].

Definition at line 56 of file TargetRegisterInfo.h.

◆ CoveredBySubRegs

const bool llvm::TargetRegisterClass::CoveredBySubRegs

◆ GlobalPriority

const bool llvm::TargetRegisterClass::GlobalPriority

◆ HasDisjunctSubRegs

const bool llvm::TargetRegisterClass::HasDisjunctSubRegs

◆ LaneMask

◆ MC

◆ OrderFunc

◆ SubClassMask

◆ SuperClasses

◆ SuperClassesSize

◆ SuperRegIndices

◆ TSFlags

The documentation for this class was generated from the following file: