HexagonISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H

15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H

27#include

28#include

30namespace llvm {

39 CONST32_GP,

40 ADDC,

41 SUBC,

47 CALL,

48 CALLnr,

51 RET_GLUE,

53 JT,

54 CP,

57 VASL,

60 MFSHL,

61 MFSHR,

63 SSAT,

64 USAT,

65 SMUL_LOHI,

66 UMUL_LOHI,

69 USMUL_LOHI,

85 D2P,

86 P2D,

87 V2Q,

88 Q2V,

96 TL_EXTEND,

97 TL_TRUNCATE,

100

101

102

103

104

105

106

107

108

109

110

111

112

113 TYPECAST,

114

115 VALIGN,

116

117 VALIGNADDR,

118

119 ISEL,

120

121

123};

124

125}

126

127

128class HexagonSubtarget;

129

131 int VarArgsFrameOffset;

134

135public:

138

139

140

141

143 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,

147

150 unsigned Intrinsic) const override;

151

154

157 bool isCtlzFast() const override { return true; }

158

160

162

164

166

167

168

169

170

172 EVT) const override;

173

174

176 unsigned DefinedValues) const override;

178 unsigned Index) const override;

179

181

185

191

193 std::pair<MVT, unsigned>

195 EVT VT) const;

196

215

240 unsigned ReturnReg, unsigned char OperandGlues) const;

242

252

258

263

268

270

272

275

278 EVT &IntermediateVT,

279 unsigned &NumIntermediates,

280 MVT &RegisterVT) const override;

281

283 EVT VT) const override;

284

285

288 return Hexagon::R0;

289 }

290

291

292

295 return Hexagon::R1;

296 }

297

302

304 EVT VT) const override {

306 return MVT::i1;

307 else

309 }

310

315

317

318 std::pair<unsigned, const TargetRegisterClass *>

320 StringRef Constraint, MVT VT) const override;

321

322

325

326

327

328

329

331 Type *Ty, unsigned AS,

333

334

336

338 bool ForCodeSize) const override;

339

340

341

342

343

345

347 const AttributeList &FuncAttributes) const override;

348

350 unsigned AddrSpace, Align Alignment,

352 unsigned *Fast) const override;

353

357 unsigned *Fast) const override;

358

359

361 const override;

362

363

364

366 Type *Ty) const override;

367

369 std::optional ByteOffset) const override;

370

373

374

383

389

390private:

391 void initializeHVXLowering();

392 unsigned getPreferredHvxVectorAction(MVT VecTy) const;

393 unsigned getCustomHvxOperationAction(SDNode &Op) const;

394

395 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,

398

399 std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;

400

425

427 if (Op.isMachineOpcode())

428 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;

430 }

431 SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,

433 SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);

435 }

436 SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;

437

438 using VectorPair = std::pair<SDValue, SDValue>;

439 using TypePair = std::pair<MVT, MVT>;

440

442 const SDLoc &dl, SelectionDAG &DAG) const;

443

445 return Op.getValueType().getSimpleVT();

446 }

447 TypePair ty(const VectorPair &Ops) const {

448 return { Ops.first.getValueType().getSimpleVT(),

449 Ops.second.getValueType().getSimpleVT() };

450 }

451 MVT tyScalar(MVT Ty) const {

452 if (!Ty.isVector())

453 return Ty;

455 }

456 MVT tyVector(MVT Ty, MVT ElemTy) const {

457 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)

458 return Ty;

459 unsigned TyWidth = Ty.getSizeInBits();

460 unsigned ElemWidth = ElemTy.getSizeInBits();

461 assert((TyWidth % ElemWidth) == 0);

463 }

464

465 MVT typeJoin(const TypePair &Tys) const;

466 TypePair typeSplit(MVT Ty) const;

467 MVT typeExtElem(MVT VecTy, unsigned Factor) const;

468 MVT typeTruncElem(MVT VecTy, unsigned Factor) const;

469 TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const;

470 TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const;

471 MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const;

472 MVT typeWidenToHvx(MVT Ty) const;

473

474 SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,

475 SelectionDAG &DAG) const;

476 VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;

477 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;

478

480 MVT Ty = ty(V);

481 const SDLoc &dl(V);

482 if (!Ty.isVector()) {

483 assert(Ty.getSizeInBits() == 64);

484 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V);

485 }

486 MVT HalfTy = typeSplit(Ty).first;

487 SDValue Idx = getZero(dl, MVT::i32, DAG);

489 }

491 MVT Ty = ty(V);

492 const SDLoc &dl(V);

493 if (!Ty.isVector()) {

494 assert(Ty.getSizeInBits() == 64);

495 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V);

496 }

497 MVT HalfTy = typeSplit(Ty).first;

498 SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32);

500 }

501

503 unsigned *Fast) const;

504 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,

506 unsigned *Fast) const;

507 void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const;

508

509 bool isHvxSingleTy(MVT Ty) const;

510 bool isHvxPairTy(MVT Ty) const;

511 bool isHvxBoolTy(MVT Ty) const;

512 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,

513 SelectionDAG &DAG) const;

514 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;

516 ArrayRef Mask, SelectionDAG &DAG) const;

517

519 MVT VecTy, SelectionDAG &DAG) const;

521 MVT VecTy, SelectionDAG &DAG) const;

522 SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,

523 unsigned BitBytes, bool ZeroFill,

524 SelectionDAG &DAG) const;

526 MVT ResTy, SelectionDAG &DAG) const;

528 MVT ResTy, SelectionDAG &DAG) const;

530 const SDLoc &dl, SelectionDAG &DAG) const;

532 const SDLoc &dl, SelectionDAG &DAG) const;

534 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)

535 const;

537 MVT ResTy, SelectionDAG &DAG) const;

539 const SDLoc &dl, SelectionDAG &DAG) const;

541 const SDLoc &dl, SelectionDAG &DAG) const;

542 SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,

543 bool ZeroExt, SelectionDAG &DAG) const;

544 SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy,

545 SelectionDAG &DAG) const;

547 SelectionDAG &DAG) const;

548 SDValue extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx,

549 SelectionDAG &DAG) const;

550 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl,

551 bool Signed, SelectionDAG &DAG) const;

552 VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed,

553 SelectionDAG &DAG) const;

555 SelectionDAG &DAG) const;

557 const SDLoc &dl, SelectionDAG &DAG) const;

559 const SDLoc &dl, SelectionDAG &DAG) const;

560

561 SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;

562 SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const;

563 SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;

564 SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;

565 SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;

566 SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;

567 SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;

568 SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;

570 SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;

571 SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;

574 SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const;

578 SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const;

579 SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;

580 SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;

581 SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;

582 SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;

583 SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;

584 SDValue LowerHvxPred32ToFp(SDValue Op, SelectionDAG &DAG) const;

585 SDValue LowerHvxPred64ToFp(SDValue Op, SelectionDAG &DAG) const;

586 SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;

587 SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;

588

589 VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const;

590

595 SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const;

596 SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const;

597 SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const;

598

599 SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;

600 SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;

601

602 std::pair<const TargetRegisterClass*, uint8_t>

603 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)

604 const override;

605

606 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const;

607 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const;

608 bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const;

609 SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;

610 void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl &Results,

611 SelectionDAG &DAG) const;

612 void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl &Results,

613 SelectionDAG &DAG) const;

614

617 const;

619 const;

620

622};

623

624}

625

626#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static bool isUndef(const MachineInstr &MI)

static Value * extractVector(IRBuilderTy &IRB, Value *V, unsigned BeginIndex, unsigned EndIndex, const Twine &Name)

static Value * insertVector(IRBuilderTy &IRB, Value *Old, Value *V, unsigned BeginIndex, const Twine &Name)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

This class represents a function call, abstracting a target machine's calling convention.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override

Returns relocation base for the given PIC jumptable.

SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const

SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const

SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const

bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override

Return if the target supports combining a chain like:

bool isCtlzFast() const override

Return true if ctlz instruction is fast.

Definition HexagonISelLowering.h:157

SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const

void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

bool isTargetCanonicalConstantNode(SDValue Op) const override

Returns true if the given Opc is considered a canonical constant for the target, which should not be ...

ConstraintType getConstraintType(StringRef Constraint) const override

Given a constraint, return the type of constraint it is for this target.

bool isTruncateFree(Type *Ty1, Type *Ty2) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const

SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const

SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const

SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const

Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

bool isLegalICmpImmediate(int64_t Imm) const override

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...

bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset) const override

Return true if it is profitable to reduce a load to a smaller type.

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...

SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const

AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandGlues) const

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const

bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...

SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const

SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const

SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const

unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override

Certain targets such as MIPS require that some types such as vectors are always broken down into scal...

SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const

bool isCheapToSpeculateCtlz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition HexagonISelLowering.h:156

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.

bool mayBeEmittedAsTailCall(const CallInst *CI) const override

Return true if the target may be able emit the call instruction as a tail call.

AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

bool isCheapToSpeculateCttz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

Definition HexagonISelLowering.h:155

bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override

Return true if result of the specified node is used by a return node only.

SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const

LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...

SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const

SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const

bool softPromoteHalfType() const override

Definition HexagonISelLowering.h:388

SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const

bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override

Return true if the target supports a memory access of this type for the given address space and align...

SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const

bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...

SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const

SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const

SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const

SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...

LegalizeAction getCustomOperationAction(SDNode &Op) const override

How to legalize this custom operation?

SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const

SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const

bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...

SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const

SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const

bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override

bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const

SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const

SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override

Determine if the target supports unaligned memory accesses.

const char * getTargetNodeName(unsigned Opcode) const override

This method returns the name of a target specific DAG node.

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Definition HexagonISelLowering.h:385

SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const

SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const

SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const

EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override

Return the ValueType of the result of SETCC operations.

Definition HexagonISelLowering.h:303

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked when a node result type is illegal for the target, and the operation was reg...

If a physical register, this returns the register that receives the exception address on entry to an ...

Definition HexagonISelLowering.h:287

Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override

Perform a store-conditional operation to Addr.

bool hasBitTest(SDValue X, SDValue Y) const override

Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...

HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)

SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.

SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const

void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...

SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const

SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const

SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const

SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const

AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override

Return true if an FMA operation is faster than a pair of mul and add instructions.

SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const

If a physical register, this returns the register that receives the exception typeid on entry to a la...

Definition HexagonISelLowering.h:294

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

Returns the target specific optimal type for load and store operations as a result of memset,...

SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const

LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Return the preferred vector type legalization action.

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const

Return the register ID of the name passed in.

std::pair< MVT, unsigned > handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget, EVT VT) const

SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const

SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const

SDValue LowerREADSTEADYCOUNTER(SDValue Op, SelectionDAG &DAG) const

Common base class shared among various IRBuilders.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

static MVT getVectorVT(MVT VT, unsigned NumElements)

static MVT getIntegerVT(unsigned BitWidth)

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

NodeType

Definition HexagonISelLowering.h:35

@ SUBC

Definition HexagonISelLowering.h:41

@ V2Q

Definition HexagonISelLowering.h:87

@ MFSHR

Definition HexagonISelLowering.h:61

@ TC_RETURN

Definition HexagonISelLowering.h:77

@ PTRUE

Definition HexagonISelLowering.h:83

@ MFSHL

Definition HexagonISelLowering.h:60

@ ISEL

Definition HexagonISelLowering.h:119

@ CALL

Definition HexagonISelLowering.h:47

@ DCFETCH

Definition HexagonISelLowering.h:79

@ USMUL_LOHI

Definition HexagonISelLowering.h:69

@ READTIMER

Definition HexagonISelLowering.h:81

@ THREAD_POINTER

Definition HexagonISelLowering.h:82

@ CP

Definition HexagonISelLowering.h:54

@ D2P

Definition HexagonISelLowering.h:85

@ VASR

Definition HexagonISelLowering.h:58

@ CALLR

Definition HexagonISelLowering.h:49

@ SMUL_LOHI

Definition HexagonISelLowering.h:65

@ OP_BEGIN

Definition HexagonISelLowering.h:36

@ COMBINE

Definition HexagonISelLowering.h:56

@ UMUL_LOHI

Definition HexagonISelLowering.h:66

@ VROR

Definition HexagonISelLowering.h:76

@ INSERT

Definition HexagonISelLowering.h:72

@ P2D

Definition HexagonISelLowering.h:86

@ Q2V

Definition HexagonISelLowering.h:88

@ ADDC

Definition HexagonISelLowering.h:40

@ TL_TRUNCATE

Definition HexagonISelLowering.h:97

@ JT

Definition HexagonISelLowering.h:53

@ VLSR

Definition HexagonISelLowering.h:59

@ CALLnr

Definition HexagonISelLowering.h:48

@ OP_END

Definition HexagonISelLowering.h:122

@ RET_GLUE

Definition HexagonISelLowering.h:51

@ VALIGNADDR

Definition HexagonISelLowering.h:117

@ VASL

Definition HexagonISelLowering.h:57

@ USAT

Definition HexagonISelLowering.h:64

@ BARRIER

Definition HexagonISelLowering.h:52

@ QTRUE

Definition HexagonISelLowering.h:93

@ QFALSE

Definition HexagonISelLowering.h:94

@ VEXTRACTW

Definition HexagonISelLowering.h:74

@ QCAT

Definition HexagonISelLowering.h:92

@ VALIGN

Definition HexagonISelLowering.h:115

@ TL_EXTEND

Definition HexagonISelLowering.h:96

@ PFALSE

Definition HexagonISelLowering.h:84

@ TYPECAST

Definition HexagonISelLowering.h:113

@ CONST32

Definition HexagonISelLowering.h:38

@ SSAT

Definition HexagonISelLowering.h:63

@ ALLOCA

Definition HexagonISelLowering.h:42

@ EXTRACTU

Definition HexagonISelLowering.h:73

@ EH_RETURN

Definition HexagonISelLowering.h:78

@ CONST32_GP

Definition HexagonISelLowering.h:39

@ READCYCLE

Definition HexagonISelLowering.h:80

@ TSTBIT

Definition HexagonISelLowering.h:71

@ AT_GOT

Definition HexagonISelLowering.h:44

@ AT_PCREL

Definition HexagonISelLowering.h:45

@ VINSERTW0

Definition HexagonISelLowering.h:75

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ UNDEF

UNDEF - An undefined node.

@ EXTRACT_SUBVECTOR

EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

LoadExtType

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI Value * getSplatValue(const Value *V)

Get splat value if the input is a splat vector or return nullptr.

AtomicOrdering

Atomic ordering for LLVM's memory model.

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

This struct is a compact representation of a valid (non-zero power of two) alignment.

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

bool isVector() const

Return true if this is a vector value type.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

This structure contains all information that is necessary for lowering calls.