LLVM: lib/Target/Hexagon/HexagonInstrInfo.cpp File Reference (original) (raw)

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Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
namespace llvm::HexagonFUnits
Macros
#define DEBUG_TYPE "hexagon-instrinfo"
#define GET_INSTRINFO_CTOR_DTOR
#define GET_INSTRMAP_INFO
Functions
bool llvm::HexagonFUnits::isSlot0Only (unsigned units)
static bool isIntRegForSubInst (Register Reg)
static bool isDblRegForSubInst (Register Reg, const HexagonRegisterInfo &HRI)
static unsigned nonDbgMICount (MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
Calculate number of instructions excluding the debug instructions.
static void parseOperands (const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
Gather register def/uses from MI.
static bool isDuplexPairMatch (unsigned Ga, unsigned Gb)
static void getLiveInRegsAt (LivePhysRegs &Regs, const MachineInstr &MI)
static void getLiveOutRegsAt (LivePhysRegs &Regs, const MachineInstr &MI)
Variables
cl::opt< bool > ScheduleInlineAsm ("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
static cl::opt< bool > EnableBranchPrediction ("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static cl::opt< bool > DisableNVSchedule ("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))
static cl::opt< bool > EnableTimingClassLatency ("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
static cl::opt< bool > EnableALUForwarding ("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
static cl::opt< bool > EnableACCForwarding ("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static cl::opt< bool > BranchRelaxAsmLarge ("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))
static cl::opt< bool > UseDFAHazardRec ("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))
const int Hexagon_MEMW_OFFSET_MAX = 4095
Constants for Hexagon instructions.
const int Hexagon_MEMW_OFFSET_MIN = -4096
const int Hexagon_MEMD_OFFSET_MAX = 8191
const int Hexagon_MEMD_OFFSET_MIN = -8192
const int Hexagon_MEMH_OFFSET_MAX = 2047
const int Hexagon_MEMH_OFFSET_MIN = -2048
const int Hexagon_MEMB_OFFSET_MAX = 1023
const int Hexagon_MEMB_OFFSET_MIN = -1024
const int Hexagon_ADDI_OFFSET_MAX = 32767
const int Hexagon_ADDI_OFFSET_MIN = -32768

◆ DEBUG_TYPE

#define DEBUG_TYPE "hexagon-instrinfo"

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

◆ getLiveInRegsAt()

◆ getLiveOutRegsAt()

◆ isDblRegForSubInst()

◆ isDuplexPairMatch()

◆ isIntRegForSubInst()

◆ nonDbgMICount()

◆ parseOperands()

◆ BranchRelaxAsmLarge

cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm")) ( "branch-relax-asm-large" , cl::init(true) , cl::Hidden , cl::desc("branch relax asm") ) static

◆ DisableNVSchedule

cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores.")) ( "disable-hexagon-nv-schedule" , cl::Hidden , cl::desc("Disable schedule adjustment for new value stores.") ) static

◆ EnableACCForwarding

cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding")) ( "enable-acc-forwarding" , cl::Hidden , cl::init(true) , cl::desc("Enable vec acc forwarding") ) static

◆ EnableALUForwarding

cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding")) ( "enable-alu-forwarding" , cl::Hidden , cl::init(true) , cl::desc("Enable vec alu forwarding") ) static

◆ EnableBranchPrediction

cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction")) ( "hexagon-enable-branch-prediction" , cl::Hidden , cl::init(true) , cl::desc("Enable branch prediction") ) static

◆ EnableTimingClassLatency

cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency")) ( "enable-timing-class-latency" , cl::Hidden , cl::init(false) , cl::desc("Enable timing class latency") ) static

◆ Hexagon_ADDI_OFFSET_MAX

const int Hexagon_ADDI_OFFSET_MAX = 32767

◆ Hexagon_ADDI_OFFSET_MIN

const int Hexagon_ADDI_OFFSET_MIN = -32768

◆ Hexagon_MEMB_OFFSET_MAX

const int Hexagon_MEMB_OFFSET_MAX = 1023

◆ Hexagon_MEMB_OFFSET_MIN

const int Hexagon_MEMB_OFFSET_MIN = -1024

◆ Hexagon_MEMD_OFFSET_MAX

const int Hexagon_MEMD_OFFSET_MAX = 8191

◆ Hexagon_MEMD_OFFSET_MIN

const int Hexagon_MEMD_OFFSET_MIN = -8192

◆ Hexagon_MEMH_OFFSET_MAX

const int Hexagon_MEMH_OFFSET_MAX = 2047

◆ Hexagon_MEMH_OFFSET_MIN

const int Hexagon_MEMH_OFFSET_MIN = -2048

◆ Hexagon_MEMW_OFFSET_MAX

const int Hexagon_MEMW_OFFSET_MAX = 4095

◆ Hexagon_MEMW_OFFSET_MIN

const int Hexagon_MEMW_OFFSET_MIN = -4096

◆ ScheduleInlineAsm

cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary.")) ( "hexagon-sched-inline-asm" ,
cl::Hidden ,
cl::init(false) ,
cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary.") )

◆ UseDFAHazardRec

cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer.")) ( "dfa-hazard-rec" , cl::init(true) , cl::Hidden , cl::desc("Use the DFA based hazard recognizer.") ) static