LLVM: lib/Target/Hexagon/HexagonInstrInfo.cpp Source File (original) (raw)
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55#include
56#include
57#include
58#include
59#include
60#include
61#include
62#include
63
64using namespace llvm;
65
66#define DEBUG_TYPE "hexagon-instrinfo"
67
68#define GET_INSTRINFO_CTOR_DTOR
69#define GET_INSTRMAP_INFO
71#include "HexagonGenDFAPacketizer.inc"
72#include "HexagonGenInstrInfo.inc"
73
75 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
76 "packetization boundary."));
77
80
82 "disable-hexagon-nv-schedule", cl::Hidden,
83 cl::desc("Disable schedule adjustment for new value stores."));
84
87 cl::desc("Enable timing class latency"));
88
91 cl::desc("Enable vec alu forwarding"));
92
95 cl::desc("Enable vec acc forwarding"));
96
99 cl::desc("branch relax asm"));
100
103 cl::desc("Use the DFA based hazard recognizer."));
104
105
116
117
118void HexagonInstrInfo::anchor() {}
119
122 Hexagon::ADJCALLSTACKUP),
123 RegInfo(ST.getHwMode()), Subtarget(ST) {}
124
125namespace llvm {
129}
130
132 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
133 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
134}
135
140
141
144 unsigned Count = 0;
145 for (; MIB != MIE; ++MIB) {
146 if (!MIB->isDebugInstr())
148 }
150}
151
152
153
154
156
157 if (!(MI.getMF()->getFunction().hasOptSize()))
158 return MI.isAsCheapAsAMove();
159
160 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
161 auto Op = MI.getOperand(1);
162
163
164 if (Op.isGlobal())
165 return false;
166
167
168 if (Op.isImm()) {
169 int64_t Imm = Op.getImm();
171 return false;
172 }
173 }
174 return MI.isAsCheapAsAMove();
175}
176
177
178
179
180
181
182
183
184
185
187
188
189 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
190 return false;
191 return true;
192}
193
194
195
196
197
201 unsigned LOOPi;
202 unsigned LOOPr;
203 if (EndLoopOp == Hexagon::ENDLOOP0) {
204 LOOPi = Hexagon::J2_loop0i;
205 LOOPr = Hexagon::J2_loop0r;
206 } else {
207 LOOPi = Hexagon::J2_loop1i;
208 LOOPr = Hexagon::J2_loop1r;
209 }
210
211
213
214 if (!Visited.insert(PB).second)
215 continue;
216 if (PB == BB)
217 continue;
219 unsigned Opc = I.getOpcode();
220 if (Opc == LOOPi || Opc == LOOPr)
221 return &I;
222
223
224 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
225 return nullptr;
226 }
227
230 }
231 return nullptr;
232}
233
234
235
236
240 Uses.clear();
241
243 if (!MO.isReg())
244 continue;
245
247 if ()
248 continue;
249
250 if (MO.isUse())
251 Uses.push_back(MO.getReg());
252
253 if (MO.isDef())
255 }
256}
257
258
260 switch (Ga) {
262 default:
263 return false;
280 }
281 return false;
282}
283
284
285
286
287
288
290 int &FrameIndex) const {
291 switch (MI.getOpcode()) {
292 default:
293 break;
294 case Hexagon::L2_loadri_io:
295 case Hexagon::L2_loadrd_io:
296 case Hexagon::V6_vL32b_ai:
297 case Hexagon::V6_vL32b_nt_ai:
298 case Hexagon::V6_vL32Ub_ai:
299 case Hexagon::LDriw_pred:
300 case Hexagon::LDriw_ctr:
301 case Hexagon::PS_vloadrq_ai:
302 case Hexagon::PS_vloadrw_ai:
303 case Hexagon::PS_vloadrw_nt_ai: {
305 if (!OpFI.isFI())
306 return 0;
308 if (!OpOff.isImm() || OpOff.getImm() != 0)
309 return 0;
310 FrameIndex = OpFI.getIndex();
311 return MI.getOperand(0).getReg();
312 }
313
314 case Hexagon::L2_ploadrit_io:
315 case Hexagon::L2_ploadrif_io:
316 case Hexagon::L2_ploadrdt_io:
317 case Hexagon::L2_ploadrdf_io: {
319 if (!OpFI.isFI())
320 return 0;
322 if (!OpOff.isImm() || OpOff.getImm() != 0)
323 return 0;
324 FrameIndex = OpFI.getIndex();
325 return MI.getOperand(0).getReg();
326 }
327 }
328
329 return 0;
330}
331
332
333
334
335
336
338 int &FrameIndex) const {
339 switch (MI.getOpcode()) {
340 default:
341 break;
342 case Hexagon::S2_storerb_io:
343 case Hexagon::S2_storerh_io:
344 case Hexagon::S2_storeri_io:
345 case Hexagon::S2_storerd_io:
346 case Hexagon::V6_vS32b_ai:
347 case Hexagon::V6_vS32Ub_ai:
348 case Hexagon::STriw_pred:
349 case Hexagon::STriw_ctr:
350 case Hexagon::PS_vstorerq_ai:
351 case Hexagon::PS_vstorerw_ai: {
353 if (!OpFI.isFI())
354 return 0;
356 if (!OpOff.isImm() || OpOff.getImm() != 0)
357 return 0;
358 FrameIndex = OpFI.getIndex();
359 return MI.getOperand(2).getReg();
360 }
361
362 case Hexagon::S2_pstorerbt_io:
363 case Hexagon::S2_pstorerbf_io:
364 case Hexagon::S2_pstorerht_io:
365 case Hexagon::S2_pstorerhf_io:
366 case Hexagon::S2_pstorerit_io:
367 case Hexagon::S2_pstorerif_io:
368 case Hexagon::S2_pstorerdt_io:
369 case Hexagon::S2_pstorerdf_io: {
371 if (!OpFI.isFI())
372 return 0;
374 if (!OpOff.isImm() || OpOff.getImm() != 0)
375 return 0;
376 FrameIndex = OpFI.getIndex();
377 return MI.getOperand(3).getReg();
378 }
379 }
380
381 return 0;
382}
383
384
385
386
390 if (MI.isBundle()) {
393 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
395 return true;
396 return false;
397 }
398
400}
401
402
403
404
408 if (MI.isBundle()) {
411 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
413 return true;
414 return false;
415 }
416
418}
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
439 bool AllowModify) const {
440 TBB = nullptr;
441 FBB = nullptr;
442 Cond.clear();
443
444
446 if (I == MBB.instr_begin())
447 return false;
448
449
450
451
452
453
454
455
456
457
458
459
460
461 do {
462 --I;
463 if (I->isEHLabel())
464
465 return true;
466 } while (I != MBB.instr_begin());
467
469 --I;
470
471 while (I->isDebugInstr()) {
472 if (I == MBB.instr_begin())
473 return false;
474 --I;
475 }
476
477 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
478 I->getOperand(0).isMBB();
479
480 if (AllowModify && JumpToBlock &&
481 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
482 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
483 I->eraseFromParent();
485 if (I == MBB.instr_begin())
486 return false;
487 --I;
488 }
489 if (!isUnpredicatedTerminator(*I))
490 return false;
491
492
495
496 while (true) {
497 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
498 if (!SecondLastInst)
499 SecondLastInst = &*I;
500 else
501
502 return true;
503 }
504 if (I == MBB.instr_begin())
505 break;
506 --I;
507 }
508
509 int LastOpcode = LastInst->getOpcode();
510 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
511
512
513 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
514 return true;
515 if (SecLastOpcode == Hexagon::J2_jump &&
517 return true;
518
520 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
521
522 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
523 return true;
524
525
526 if (LastInst && !SecondLastInst) {
527 if (LastOpcode == Hexagon::J2_jump) {
529 return false;
530 }
535 return false;
536 }
537 if (LastOpcodeHasJMP_c) {
541 return false;
542 }
543
549 return false;
550 }
552 << " with one jump\n";);
553
554 return true;
555 }
556
558 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
559 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
561 return true;
566 return false;
567 }
568
569
570 if (SecLastOpcodeHasNVJump &&
572 (LastOpcode == Hexagon::J2_jump)) {
578 return false;
579 }
580
581
582
583 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
586 if (AllowModify)
587 I->eraseFromParent();
588 return false;
589 }
590
591
592 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
597 return false;
598 }
600 << " with two jumps";);
601
602 return true;
603}
604
606 int *BytesRemoved) const {
607 assert(!BytesRemoved && "code size not handled");
608
611 unsigned Count = 0;
612 while (I != MBB.begin()) {
613 --I;
614 if (I->isDebugInstr())
615 continue;
616
617 if (->isBranch())
619 if (Count && (I->getOpcode() == Hexagon::J2_jump))
620 llvm_unreachable("Malformed basic block: unconditional branch not last");
624 }
626}
627
633 int *BytesAdded) const {
634 unsigned BOpc = Hexagon::J2_jump;
635 unsigned BccOpc = Hexagon::J2_jumpt;
637 assert(TBB && "insertBranch must not be told to insert a fallthrough");
638 assert(!BytesAdded && "code size not handled");
639
640
641
642
643 if (.empty() && Cond[0].isImm())
644 BccOpc = Cond[0].getImm();
645
646 if (!FBB) {
647 if (Cond.empty()) {
648
649
650
651
654 auto Term = MBB.getFirstTerminator();
661 }
664 int EndLoopOp = Cond[0].getImm();
666
667
670 VisitedBBs);
671 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
672 Loop->getOperand(0).setMBB(TBB);
673
676 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
677
678
679
687 } else if(Cond[2].isImm()) {
690 } else
692 } else {
693 assert((Cond.size() == 2) && "Malformed cond vector");
697 }
698 return 1;
699 }
701 "Cond. cannot be empty when multiple branchings are required");
703 "NV-jump cannot be inserted with another branch");
704
706 int EndLoopOp = Cond[0].getImm();
708
709
712 VisitedBBs);
713 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
714 Loop->getOperand(0).setMBB(TBB);
715
717 } else {
721 }
723
724 return 2;
725}
726
727namespace {
732 int64_t TripCount;
735
736public:
741
742
743 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
744 ? -1
745 : Loop->getOperand(1).getImm();
746 if (TripCount == -1)
747 LoopCount = Loop->getOperand(1).getReg();
748 }
749
750 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
751
752 return MI == EndLoop;
753 }
754
755 std::optional createTripCountGreaterCondition(
756 int TC, MachineBasicBlock &MBB,
757 SmallVectorImpl &Cond) override {
758 if (TripCount == -1) {
759
767 return {};
768 }
769
770 return TripCount > TC;
771 }
772
773 void setPreheader(MachineBasicBlock *NewPreheader) override {
775 Loop);
776 }
777
778 void adjustTripCount(int TripCountAdjust) override {
779
780
781 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
782 Loop->getOpcode() == Hexagon::J2_loop1i) {
783 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
784 assert(TripCount > 0 && "Can't create an empty or negative loop!");
786 return;
787 }
788
789
790
792 Register NewLoopCount = TII->createVR(MF, MVT::i32);
794 TII->get(Hexagon::A2_addi), NewLoopCount)
796 .addImm(TripCountAdjust);
798 }
799
800 void disposed(LiveIntervals *LIS) override {
801 if (LIS)
804 }
805};
806}
807
808std::unique_ptrTargetInstrInfo::PipelinerLoopInfo
810
812
816 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
817 if (LoopInst)
818 return std::make_unique(LoopInst, &*I);
819 }
820 return nullptr;
821}
822
824 unsigned NumCycles, unsigned ExtraPredCycles,
827}
828
835
838 return NumInstrs <= 4;
839}
840
846 for (auto I = B.begin(); I != E; ++I) {
847 Clobbers.clear();
849 }
850}
851
856 for (auto I = B.rbegin(); I != E; ++I)
858}
859
863 Register SrcReg, bool KillSrc,
864 bool RenamableDest,
865 bool RenamableSrc) const {
868
869 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
871 .addReg(SrcReg, KillFlag);
872 return;
873 }
874 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
876 .addReg(SrcReg, KillFlag);
877 return;
878 }
879 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
880
883 return;
884 }
885 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
886 Hexagon::IntRegsRegClass.contains(SrcReg)) {
888 .addReg(SrcReg, KillFlag);
889 return;
890 }
891 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
892 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
894 .addReg(SrcReg, KillFlag);
895 return;
896 }
897 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
898 Hexagon::IntRegsRegClass.contains(SrcReg)) {
900 .addReg(SrcReg, KillFlag);
901 return;
902 }
903 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
904 Hexagon::IntRegsRegClass.contains(DestReg)) {
906 .addReg(SrcReg, KillFlag);
907 return;
908 }
909 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
910 Hexagon::PredRegsRegClass.contains(DestReg)) {
912 .addReg(SrcReg, KillFlag);
913 return;
914 }
915 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
916 Hexagon::IntRegsRegClass.contains(DestReg)) {
918 .addReg(SrcReg, KillFlag);
919 return;
920 }
921 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
923 addReg(SrcReg, KillFlag);
924 return;
925 }
926 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
929 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
930 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
934 .addReg(SrcHi, KillFlag | UndefHi)
935 .addReg(SrcLo, KillFlag | UndefLo);
936 return;
937 }
938 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
941 .addReg(SrcReg, KillFlag);
942 return;
943 }
944 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
945 Hexagon::HvxVRRegClass.contains(DestReg)) {
947 return;
948 }
949 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
950 Hexagon::HvxVRRegClass.contains(SrcReg)) {
952 return;
953 }
954
955#ifndef NDEBUG
956
958 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
959#endif
961}
962
965 Register SrcReg, bool isKill, int FI,
973
977
978 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
982 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
986 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
990 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
994 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
998 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1002 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1006 } else {
1008 }
1009}
1010
1020
1024
1025 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1028 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1031 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1034 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1037 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1040 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1043 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1046 } else {
1047 llvm_unreachable("Can't store this register to stack slot");
1048 }
1049}
1050
1051
1052
1053
1054
1055
1056
1064 unsigned Opc = MI.getOpcode();
1065
1066 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1067 Register Mx = MI.getOperand(MxOp).getReg();
1068 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1070 .add(MI.getOperand((HasImm ? 5 : 4)));
1072 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1073 if (HasImm)
1074 MIB.add(MI.getOperand(4));
1077 return true;
1078 };
1079
1081 if (MI.memoperands().empty())
1082 return false;
1084 return MMO->getAlign() >= NeedAlign;
1085 });
1086 };
1087
1088 switch (Opc) {
1089 case Hexagon::PS_call_instrprof_custom: {
1090 auto Op0 = MI.getOperand(0);
1091 assert(Op0.isGlobal() &&
1092 "First operand must be a global containing handler name.");
1093 const GlobalValue *NameVar = Op0.getGlobal();
1096 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1097
1099
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1122 MIB.addExternalSymbol(cstr);
1124 return true;
1125 }
1126 case TargetOpcode::COPY: {
1132 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1133 }
1135 return true;
1136 }
1137 case Hexagon::PS_aligna:
1140 .addImm(-MI.getOperand(1).getImm());
1142 return true;
1143 case Hexagon::V6_vassignp: {
1144 Register SrcReg = MI.getOperand(1).getReg();
1145 Register DstReg = MI.getOperand(0).getReg();
1146 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1147 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1149 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1150 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1153 .addReg(SrcHi, UndefHi)
1154 .addReg(SrcLo, Kill | UndefLo);
1156 return true;
1157 }
1158 case Hexagon::V6_lo: {
1159 Register SrcReg = MI.getOperand(1).getReg();
1160 Register DstReg = MI.getOperand(0).getReg();
1161 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1164 MRI.clearKillFlags(SrcSubLo);
1165 return true;
1166 }
1167 case Hexagon::V6_hi: {
1168 Register SrcReg = MI.getOperand(1).getReg();
1169 Register DstReg = MI.getOperand(0).getReg();
1170 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1173 MRI.clearKillFlags(SrcSubHi);
1174 return true;
1175 }
1176 case Hexagon::PS_vloadrv_ai: {
1177 Register DstReg = MI.getOperand(0).getReg();
1180 int Offset = MI.getOperand(2).getImm();
1181 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1182 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1183 : Hexagon::V6_vL32Ub_ai;
1189 return true;
1190 }
1191 case Hexagon::PS_vloadrw_ai: {
1192 Register DstReg = MI.getOperand(0).getReg();
1195 int Offset = MI.getOperand(2).getImm();
1196 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1197 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1198 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1199 : Hexagon::V6_vL32Ub_ai;
1201 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1206 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1211 return true;
1212 }
1213 case Hexagon::PS_vstorerv_ai: {
1218 int Offset = MI.getOperand(1).getImm();
1219 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1220 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1221 : Hexagon::V6_vS32Ub_ai;
1228 return true;
1229 }
1230 case Hexagon::PS_vstorerw_ai: {
1231 Register SrcReg = MI.getOperand(2).getReg();
1234 int Offset = MI.getOperand(1).getImm();
1235 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1236 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1237 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1238 : Hexagon::V6_vS32Ub_ai;
1242 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1247 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1250 return true;
1251 }
1252 case Hexagon::PS_true: {
1253 Register Reg = MI.getOperand(0).getReg();
1258 return true;
1259 }
1260 case Hexagon::PS_false: {
1261 Register Reg = MI.getOperand(0).getReg();
1266 return true;
1267 }
1268 case Hexagon::PS_qtrue: {
1273 return true;
1274 }
1275 case Hexagon::PS_qfalse: {
1280 return true;
1281 }
1282 case Hexagon::PS_vdd0: {
1283 Register Vd = MI.getOperand(0).getReg();
1288 return true;
1289 }
1290 case Hexagon::PS_vmulw: {
1291
1292 Register DstReg = MI.getOperand(0).getReg();
1293 Register Src1Reg = MI.getOperand(1).getReg();
1294 Register Src2Reg = MI.getOperand(2).getReg();
1295 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1296 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1297 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1298 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1300 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1304 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1308 MRI.clearKillFlags(Src1SubHi);
1309 MRI.clearKillFlags(Src1SubLo);
1310 MRI.clearKillFlags(Src2SubHi);
1311 MRI.clearKillFlags(Src2SubLo);
1312 return true;
1313 }
1314 case Hexagon::PS_vmulw_acc: {
1315
1316 Register DstReg = MI.getOperand(0).getReg();
1317 Register Src1Reg = MI.getOperand(1).getReg();
1318 Register Src2Reg = MI.getOperand(2).getReg();
1319 Register Src3Reg = MI.getOperand(3).getReg();
1320 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1321 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1322 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1323 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1324 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1325 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1327 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1332 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1337 MRI.clearKillFlags(Src1SubHi);
1338 MRI.clearKillFlags(Src1SubLo);
1339 MRI.clearKillFlags(Src2SubHi);
1340 MRI.clearKillFlags(Src2SubLo);
1341 MRI.clearKillFlags(Src3SubHi);
1342 MRI.clearKillFlags(Src3SubLo);
1343 return true;
1344 }
1345 case Hexagon::PS_pselect: {
1358 if (Rd != Rs)
1360 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1362 if (Rd != Rt)
1367 return true;
1368 }
1369 case Hexagon::PS_vselect: {
1379
1382 : PState;
1384 .add(Op0)
1386 .add(Op2);
1387 if (IsDestLive)
1389 IsDestLive = true;
1390 }
1393 .add(Op0)
1394 .addReg(PReg, PState)
1395 .add(Op3);
1396 if (IsDestLive)
1398 }
1400 return true;
1401 }
1402 case Hexagon::PS_wselect: {
1412
1415 : PState;
1416 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1417 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1419 .add(Op0)
1423 if (IsDestLive)
1425 IsDestLive = true;
1426 }
1428 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1429 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1431 .add(Op0)
1432 .addReg(PReg, PState)
1435 if (IsDestLive)
1437 }
1439 return true;
1440 }
1441
1442 case Hexagon::PS_crash: {
1443
1445 public:
1448
1450 return false;
1451 }
1453 return false;
1454 }
1456 return false;
1457 }
1458 void printCustom(raw_ostream &OS) const override {
1459 OS << "MisalignedCrash";
1460 }
1461 };
1462
1463 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1469 .addImm(0xBADC0FEE)
1472 return true;
1473 }
1474
1475 case Hexagon::PS_tailcall_i:
1476 MI.setDesc(get(Hexagon::J2_jump));
1477 return true;
1478 case Hexagon::PS_tailcall_r:
1479 case Hexagon::PS_jmpret:
1480 MI.setDesc(get(Hexagon::J2_jumpr));
1481 return true;
1482 case Hexagon::PS_jmprett:
1483 MI.setDesc(get(Hexagon::J2_jumprt));
1484 return true;
1485 case Hexagon::PS_jmpretf:
1486 MI.setDesc(get(Hexagon::J2_jumprf));
1487 return true;
1488 case Hexagon::PS_jmprettnewpt:
1489 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1490 return true;
1491 case Hexagon::PS_jmpretfnewpt:
1492 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1493 return true;
1494 case Hexagon::PS_jmprettnew:
1495 MI.setDesc(get(Hexagon::J2_jumprtnew));
1496 return true;
1497 case Hexagon::PS_jmpretfnew:
1498 MI.setDesc(get(Hexagon::J2_jumprfnew));
1499 return true;
1500
1501 case Hexagon::PS_loadrub_pci:
1502 return RealCirc(Hexagon::L2_loadrub_pci, true, 4);
1503 case Hexagon::PS_loadrb_pci:
1504 return RealCirc(Hexagon::L2_loadrb_pci, true, 4);
1505 case Hexagon::PS_loadruh_pci:
1506 return RealCirc(Hexagon::L2_loadruh_pci, true, 4);
1507 case Hexagon::PS_loadrh_pci:
1508 return RealCirc(Hexagon::L2_loadrh_pci, true, 4);
1509 case Hexagon::PS_loadri_pci:
1510 return RealCirc(Hexagon::L2_loadri_pci, true, 4);
1511 case Hexagon::PS_loadrd_pci:
1512 return RealCirc(Hexagon::L2_loadrd_pci, true, 4);
1513 case Hexagon::PS_loadrub_pcr:
1514 return RealCirc(Hexagon::L2_loadrub_pcr, false, 3);
1515 case Hexagon::PS_loadrb_pcr:
1516 return RealCirc(Hexagon::L2_loadrb_pcr, false, 3);
1517 case Hexagon::PS_loadruh_pcr:
1518 return RealCirc(Hexagon::L2_loadruh_pcr, false, 3);
1519 case Hexagon::PS_loadrh_pcr:
1520 return RealCirc(Hexagon::L2_loadrh_pcr, false, 3);
1521 case Hexagon::PS_loadri_pcr:
1522 return RealCirc(Hexagon::L2_loadri_pcr, false, 3);
1523 case Hexagon::PS_loadrd_pcr:
1524 return RealCirc(Hexagon::L2_loadrd_pcr, false, 3);
1525 case Hexagon::PS_storerb_pci:
1526 return RealCirc(Hexagon::S2_storerb_pci, true, 3);
1527 case Hexagon::PS_storerh_pci:
1528 return RealCirc(Hexagon::S2_storerh_pci, true, 3);
1529 case Hexagon::PS_storerf_pci:
1530 return RealCirc(Hexagon::S2_storerf_pci, true, 3);
1531 case Hexagon::PS_storeri_pci:
1532 return RealCirc(Hexagon::S2_storeri_pci, true, 3);
1533 case Hexagon::PS_storerd_pci:
1534 return RealCirc(Hexagon::S2_storerd_pci, true, 3);
1535 case Hexagon::PS_storerb_pcr:
1536 return RealCirc(Hexagon::S2_storerb_pcr, false, 2);
1537 case Hexagon::PS_storerh_pcr:
1538 return RealCirc(Hexagon::S2_storerh_pcr, false, 2);
1539 case Hexagon::PS_storerf_pcr:
1540 return RealCirc(Hexagon::S2_storerf_pcr, false, 2);
1541 case Hexagon::PS_storeri_pcr:
1542 return RealCirc(Hexagon::S2_storeri_pcr, false, 2);
1543 case Hexagon::PS_storerd_pcr:
1544 return RealCirc(Hexagon::S2_storerd_pcr, false, 2);
1545 }
1546
1547 return false;
1548}
1549
1554 unsigned Opc = MI.getOpcode();
1556
1557 switch (Opc) {
1558 case Hexagon::V6_vgather_vscatter_mh_pseudo:
1559
1568 .addReg(Hexagon::VTMP);
1570 return First.getInstrIterator();
1571 case Hexagon::V6_vgathermh_pseudo:
1578 .addImm(MI.getOperand(1).getImm())
1579 .addReg(Hexagon::VTMP);
1581 return First.getInstrIterator();
1582
1583 case Hexagon::V6_vgathermw_pseudo:
1590 .addImm(MI.getOperand(1).getImm())
1591 .addReg(Hexagon::VTMP);
1593 return First.getInstrIterator();
1594
1595 case Hexagon::V6_vgathermhw_pseudo:
1602 .addImm(MI.getOperand(1).getImm())
1603 .addReg(Hexagon::VTMP);
1605 return First.getInstrIterator();
1606
1607 case Hexagon::V6_vgathermhq_pseudo:
1615 .addImm(MI.getOperand(1).getImm())
1616 .addReg(Hexagon::VTMP);
1618 return First.getInstrIterator();
1619
1620 case Hexagon::V6_vgathermwq_pseudo:
1628 .addImm(MI.getOperand(1).getImm())
1629 .addReg(Hexagon::VTMP);
1631 return First.getInstrIterator();
1632
1633 case Hexagon::V6_vgathermhwq_pseudo:
1641 .addImm(MI.getOperand(1).getImm())
1642 .addReg(Hexagon::VTMP);
1644 return First.getInstrIterator();
1645 }
1646
1647 return MI.getIterator();
1648}
1649
1650
1651
1654 if (Cond.empty())
1655 return true;
1656 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1657 unsigned opcode = Cond[0].getImm();
1658
1659 assert(get(opcode).isBranch() && "Should be a branching condition.");
1661 return true;
1663 Cond[0].setImm(NewOpcode);
1664 return false;
1665}
1666
1672
1676
1677
1678
1679
1680
1681
1682
1683
1684
1689
1695 return false;
1696 }
1697 int Opc = MI.getOpcode();
1700
1701
1702
1703
1704
1705
1710 unsigned NOp = 0, NumOps = MI.getNumOperands();
1711 while (NOp < NumOps) {
1713 if (.isReg() ||
.isDef() || Op.isImplicit())
1714 break;
1716 NOp++;
1717 }
1718
1720 unsigned PredRegPos, PredRegFlags;
1721 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1722 (void)GotPredReg;
1724 T.addReg(PredReg, PredRegFlags);
1725 while (NOp < NumOps)
1726 T.add(MI.getOperand(NOp++));
1727
1728 MI.setDesc(get(PredOpc));
1729 while (unsigned n = MI.getNumOperands())
1730 MI.removeOperand(n-1);
1731 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1732 MI.addOperand(T->getOperand(i));
1733
1735 B.erase(TI);
1736
1738 MRI.clearKillFlags(PredReg);
1739 return true;
1740}
1741
1744
1745 return false;
1746}
1747
1749 std::vector &Pred,
1750 bool SkipDead) const {
1752
1754 if (MO.isReg()) {
1755 if (!MO.isDef())
1756 continue;
1757 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1758 if (RC == &Hexagon::PredRegsRegClass) {
1759 Pred.push_back(MO);
1760 return true;
1761 }
1762 continue;
1763 } else if (MO.isRegMask()) {
1764 for (Register PR : Hexagon::PredRegsRegClass) {
1765 if (.modifiesRegister(PR, &HRI))
1766 continue;
1767 Pred.push_back(MO);
1768 return true;
1769 }
1770 }
1771 }
1772 return false;
1773}
1774
1776 if (.getDesc().isPredicable())
1777 return false;
1778
1780 if (!Subtarget.usePredicatedCalls())
1781 return false;
1782 }
1783
1784
1785 if (!Subtarget.hasV62Ops()) {
1786 switch (MI.getOpcode()) {
1787 case Hexagon::V6_vL32b_ai:
1788 case Hexagon::V6_vL32b_pi:
1789 case Hexagon::V6_vL32b_ppu:
1790 case Hexagon::V6_vL32b_cur_ai:
1791 case Hexagon::V6_vL32b_cur_pi:
1792 case Hexagon::V6_vL32b_cur_ppu:
1793 case Hexagon::V6_vL32b_nt_ai:
1794 case Hexagon::V6_vL32b_nt_pi:
1795 case Hexagon::V6_vL32b_nt_ppu:
1796 case Hexagon::V6_vL32b_tmp_ai:
1797 case Hexagon::V6_vL32b_tmp_pi:
1798 case Hexagon::V6_vL32b_tmp_ppu:
1799 case Hexagon::V6_vL32b_nt_cur_ai:
1800 case Hexagon::V6_vL32b_nt_cur_pi:
1801 case Hexagon::V6_vL32b_nt_cur_ppu:
1802 case Hexagon::V6_vL32b_nt_tmp_ai:
1803 case Hexagon::V6_vL32b_nt_tmp_pi:
1804 case Hexagon::V6_vL32b_nt_tmp_ppu:
1805 return false;
1806 }
1807 }
1808 return true;
1809}
1810
1814
1815
1816
1817
1818
1819
1820 if (MI.isDebugInstr())
1821 return false;
1822
1823
1824 if (MI.isCall()) {
1825
1827 return true;
1828
1829
1830 for (auto *I : MBB->successors())
1831 if (I->isEHPad())
1832 return true;
1833 }
1834
1835
1836 if (MI.getDesc().isTerminator() || MI.isPosition())
1837 return true;
1838
1839
1840 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1841 return true;
1842
1844 return true;
1845
1846 return false;
1847}
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1863
1864 bool atInsnStart = true;
1865 unsigned Length = 0;
1867 for (; *Str; ++Str) {
1870 atInsnStart = true;
1871 if (atInsnStart && (static_cast<unsigned char>(*Str))) {
1872 Length += MaxInstLength;
1873 atInsnStart = false;
1874 }
1877 atInsnStart = false;
1878 }
1879
1880
1884}
1885
1893
1894
1895
1896
1897
1899 Register &SrcReg2, int64_t &Mask,
1900 int64_t &Value) const {
1901 unsigned Opc = MI.getOpcode();
1902
1903
1904 switch (Opc) {
1905 case Hexagon::C2_cmpeq:
1906 case Hexagon::C2_cmpeqp:
1907 case Hexagon::C2_cmpgt:
1908 case Hexagon::C2_cmpgtp:
1909 case Hexagon::C2_cmpgtu:
1910 case Hexagon::C2_cmpgtup:
1911 case Hexagon::C4_cmpneq:
1912 case Hexagon::C4_cmplte:
1913 case Hexagon::C4_cmplteu:
1914 case Hexagon::C2_cmpeqi:
1915 case Hexagon::C2_cmpgti:
1916 case Hexagon::C2_cmpgtui:
1917 case Hexagon::C4_cmpneqi:
1918 case Hexagon::C4_cmplteui:
1919 case Hexagon::C4_cmpltei:
1920 SrcReg = MI.getOperand(1).getReg();
1921 Mask = ~0;
1922 break;
1923 case Hexagon::A4_cmpbeq:
1924 case Hexagon::A4_cmpbgt:
1925 case Hexagon::A4_cmpbgtu:
1926 case Hexagon::A4_cmpbeqi:
1927 case Hexagon::A4_cmpbgti:
1928 case Hexagon::A4_cmpbgtui:
1929 SrcReg = MI.getOperand(1).getReg();
1930 Mask = 0xFF;
1931 break;
1932 case Hexagon::A4_cmpheq:
1933 case Hexagon::A4_cmphgt:
1934 case Hexagon::A4_cmphgtu:
1935 case Hexagon::A4_cmpheqi:
1936 case Hexagon::A4_cmphgti:
1937 case Hexagon::A4_cmphgtui:
1938 SrcReg = MI.getOperand(1).getReg();
1939 Mask = 0xFFFF;
1940 break;
1941 }
1942
1943
1944 switch (Opc) {
1945 case Hexagon::C2_cmpeq:
1946 case Hexagon::C2_cmpeqp:
1947 case Hexagon::C2_cmpgt:
1948 case Hexagon::C2_cmpgtp:
1949 case Hexagon::C2_cmpgtu:
1950 case Hexagon::C2_cmpgtup:
1951 case Hexagon::A4_cmpbeq:
1952 case Hexagon::A4_cmpbgt:
1953 case Hexagon::A4_cmpbgtu:
1954 case Hexagon::A4_cmpheq:
1955 case Hexagon::A4_cmphgt:
1956 case Hexagon::A4_cmphgtu:
1957 case Hexagon::C4_cmpneq:
1958 case Hexagon::C4_cmplte:
1959 case Hexagon::C4_cmplteu:
1960 SrcReg2 = MI.getOperand(2).getReg();
1962 return true;
1963
1964 case Hexagon::C2_cmpeqi:
1965 case Hexagon::C2_cmpgtui:
1966 case Hexagon::C2_cmpgti:
1967 case Hexagon::C4_cmpneqi:
1968 case Hexagon::C4_cmplteui:
1969 case Hexagon::C4_cmpltei:
1970 case Hexagon::A4_cmpbeqi:
1971 case Hexagon::A4_cmpbgti:
1972 case Hexagon::A4_cmpbgtui:
1973 case Hexagon::A4_cmpheqi:
1974 case Hexagon::A4_cmphgti:
1975 case Hexagon::A4_cmphgtui: {
1976 SrcReg2 = 0;
1978 if (!Op2.isImm())
1979 return false;
1980 Value = MI.getOperand(2).getImm();
1981 return true;
1982 }
1983 }
1984
1985 return false;
1986}
1987
1990 unsigned *PredCost) const {
1992}
1993
1999
2000
2001
2002
2003
2008 return false;
2009
2010
2011
2013 return true;
2014
2015
2016 unsigned BasePosA, OffsetPosA;
2018 return false;
2021 unsigned BaseSubA = BaseA.getSubReg();
2022
2023
2024 unsigned BasePosB, OffsetPosB;
2026 return false;
2029 unsigned BaseSubB = BaseB.getSubReg();
2030
2031 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2032 return false;
2033
2034
2037
2038
2043 return false;
2046
2047
2048
2049 if (OffsetA > OffsetB) {
2050 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2051 return SizeB <= OffDiff;
2052 }
2053 if (OffsetA < OffsetB) {
2054 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2055 return SizeA <= OffDiff;
2056 }
2057
2058 return false;
2059}
2060
2061
2063 int &Value) const {
2065 unsigned BasePos = 0, OffsetPos = 0;
2067 return false;
2071 return true;
2072 }
2073 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2075 if (AddOp.isImm()) {
2076 Value = AddOp.getImm();
2077 return true;
2078 }
2079 }
2080
2081 return false;
2082}
2083
2084std::pair<unsigned, unsigned>
2089
2093
2094 static const std::pair<unsigned, const char*> Flags[] = {
2095 {MO_PCREL, "hexagon-pcrel"},
2096 {MO_GOT, "hexagon-got"},
2097 {MO_LO16, "hexagon-lo16"},
2098 {MO_HI16, "hexagon-hi16"},
2099 {MO_GPREL, "hexagon-gprel"},
2100 {MO_GDGOT, "hexagon-gdgot"},
2101 {MO_GDPLT, "hexagon-gdplt"},
2102 {MO_IE, "hexagon-ie"},
2103 {MO_IEGOT, "hexagon-iegot"},
2104 {MO_TPREL, "hexagon-tprel"}
2105 };
2107}
2108
2112
2113 static const std::pair<unsigned, const char*> Flags[] = {
2114 {HMOTF_ConstExtended, "hexagon-ext"}
2115 };
2117}
2118
2122 if (VT == MVT::i1) {
2123 TRC = &Hexagon::PredRegsRegClass;
2124 } else if (VT == MVT::i32 || VT == MVT::f32) {
2125 TRC = &Hexagon::IntRegsRegClass;
2126 } else if (VT == MVT::i64 || VT == MVT::f64) {
2127 TRC = &Hexagon::DoubleRegsRegClass;
2128 } else {
2130 }
2131
2132 Register NewReg = MRI.createVirtualRegister(TRC);
2133 return NewReg;
2134}
2135
2139
2144
2148
2151 .getDesc().mayStore() &&
2152 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2153 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2154 (MI) &&
.isBranch() &&
.isReturn() &&
.isCall();
2155}
2156
2157
2161
2162
2163
2165 const uint64_t F = MI.getDesc().TSFlags;
2167 if (isExtended)
2168 return true;
2169
2173 return false;
2174
2175 if (MI.isCall())
2176 return false;
2177
2180
2181
2183 return true;
2184
2185
2187 return false;
2188
2189
2190
2191
2194 return true;
2195
2196
2197
2198 assert(MO.isImm() && "Extendable operand must be Immediate type");
2199
2202 int32_t SValue = Value;
2205 return SValue < MinValue || SValue > MaxValue;
2206 }
2210 return UValue < MinValue || UValue > MaxValue;
2211}
2212
2214 switch (MI.getOpcode()) {
2215 case Hexagon::L4_return:
2216 case Hexagon::L4_return_t:
2217 case Hexagon::L4_return_f:
2218 case Hexagon::L4_return_tnew_pnt:
2219 case Hexagon::L4_return_fnew_pnt:
2220 case Hexagon::L4_return_tnew_pt:
2221 case Hexagon::L4_return_fnew_pt:
2222 return true;
2223 }
2224 return false;
2225}
2226
2227
2231 return false;
2233
2238
2241
2242 for (auto &RegA : DefsA)
2243 for (auto &RegB : UsesB) {
2244
2245 if (RegA == RegB)
2246 return true;
2247
2248 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2249 return true;
2250
2251 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2252 return true;
2253 }
2254
2255 return false;
2256}
2257
2258
2260 switch (MI.getOpcode()) {
2261 case Hexagon::V6_vL32b_cur_pi:
2262 case Hexagon::V6_vL32b_cur_ai:
2263 return true;
2264 }
2265 return false;
2266}
2267
2268
2269
2272 return true;
2273
2274 return false;
2275}
2276
2277
2284
2286 return (Opcode == Hexagon::ENDLOOP0 ||
2287 Opcode == Hexagon::ENDLOOP1);
2288}
2289
2291 switch(OpType) {
2298 return true;
2299 default:
2300 return false;
2301 }
2302}
2303
2308 return true;
2309
2310
2311
2312 switch (MI.getOpcode()) {
2313
2314 case Hexagon::PS_fi:
2315 case Hexagon::PS_fia:
2316 return true;
2317 default:
2318 return false;
2319 }
2320 return false;
2321}
2322
2323
2324
2325
2327
2328 const uint64_t F = MI.getDesc().TSFlags;
2330 return true;
2331
2332
2335 return true;
2336 return false;
2337}
2338
2340 unsigned Opcode = MI.getOpcode();
2343}
2344
2345
2349 return false;
2350 if (.mayLoad() &&
.mayStore())
2351 return false;
2353}
2354
2356 switch (MI.getOpcode()) {
2357 case Hexagon::J2_callr:
2358 case Hexagon::J2_callrf:
2359 case Hexagon::J2_callrt:
2360 case Hexagon::PS_call_nr:
2361 return true;
2362 }
2363 return false;
2364}
2365
2367 switch (MI.getOpcode()) {
2368 case Hexagon::L4_return:
2369 case Hexagon::L4_return_t:
2370 case Hexagon::L4_return_f:
2371 case Hexagon::L4_return_fnew_pnt:
2372 case Hexagon::L4_return_fnew_pt:
2373 case Hexagon::L4_return_tnew_pnt:
2374 case Hexagon::L4_return_tnew_pt:
2375 return true;
2376 }
2377 return false;
2378}
2379
2381 switch (MI.getOpcode()) {
2382 case Hexagon::J2_jumpr:
2383 case Hexagon::J2_jumprt:
2384 case Hexagon::J2_jumprf:
2385 case Hexagon::J2_jumprtnewpt:
2386 case Hexagon::J2_jumprfnewpt:
2387 case Hexagon::J2_jumprtnew:
2388 case Hexagon::J2_jumprfnew:
2389 return true;
2390 }
2391 return false;
2392}
2393
2394
2395
2396
2397
2399 unsigned offset) const {
2400
2401
2404
2405 switch (MI.getOpcode()) {
2406
2407 default:
2408 return false;
2409 case Hexagon::J2_jump:
2410 case Hexagon::J2_call:
2411 case Hexagon::PS_call_nr:
2413 case Hexagon::J2_jumpt:
2414 case Hexagon::J2_jumpf:
2415 case Hexagon::J2_jumptnew:
2416 case Hexagon::J2_jumptnewpt:
2417 case Hexagon::J2_jumpfnew:
2418 case Hexagon::J2_jumpfnewpt:
2419 case Hexagon::J2_callt:
2420 case Hexagon::J2_callf:
2422 case Hexagon::J2_loop0i:
2423 case Hexagon::J2_loop0iext:
2424 case Hexagon::J2_loop0r:
2425 case Hexagon::J2_loop0rext:
2426 case Hexagon::J2_loop1i:
2427 case Hexagon::J2_loop1iext:
2428 case Hexagon::J2_loop1r:
2429 case Hexagon::J2_loop1rext:
2431
2432 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2433 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2434 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2435 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2437 }
2438}
2439
2445
2447 unsigned Opcode = MI.getOpcode();
2448 return Opcode == Hexagon::J2_loop0i ||
2449 Opcode == Hexagon::J2_loop0r ||
2450 Opcode == Hexagon::J2_loop0iext ||
2451 Opcode == Hexagon::J2_loop0rext ||
2452 Opcode == Hexagon::J2_loop1i ||
2453 Opcode == Hexagon::J2_loop1r ||
2454 Opcode == Hexagon::J2_loop1iext ||
2455 Opcode == Hexagon::J2_loop1rext;
2456}
2457
2459 switch (MI.getOpcode()) {
2460 default: return false;
2461 case Hexagon::L4_iadd_memopw_io:
2462 case Hexagon::L4_isub_memopw_io:
2463 case Hexagon::L4_add_memopw_io:
2464 case Hexagon::L4_sub_memopw_io:
2465 case Hexagon::L4_and_memopw_io:
2466 case Hexagon::L4_or_memopw_io:
2467 case Hexagon::L4_iadd_memoph_io:
2468 case Hexagon::L4_isub_memoph_io:
2469 case Hexagon::L4_add_memoph_io:
2470 case Hexagon::L4_sub_memoph_io:
2471 case Hexagon::L4_and_memoph_io:
2472 case Hexagon::L4_or_memoph_io:
2473 case Hexagon::L4_iadd_memopb_io:
2474 case Hexagon::L4_isub_memopb_io:
2475 case Hexagon::L4_add_memopb_io:
2476 case Hexagon::L4_sub_memopb_io:
2477 case Hexagon::L4_and_memopb_io:
2478 case Hexagon::L4_or_memopb_io:
2479 case Hexagon::L4_ior_memopb_io:
2480 case Hexagon::L4_ior_memoph_io:
2481 case Hexagon::L4_ior_memopw_io:
2482 case Hexagon::L4_iand_memopb_io:
2483 case Hexagon::L4_iand_memoph_io:
2484 case Hexagon::L4_iand_memopw_io:
2485 return true;
2486 }
2487 return false;
2488}
2489
2494
2499
2503
2507
2511
2516
2521
2522
2524 unsigned OperandNum) const {
2525 const uint64_t F = MI.getDesc().TSFlags;
2527 == OperandNum;
2528}
2529
2535
2541
2547
2555
2560
2565
2572
2574 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2575 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2576 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2577 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2578}
2579
2581 switch (MI.getOpcode()) {
2582
2583 case Hexagon::L2_loadrb_io:
2584 case Hexagon::L4_loadrb_ur:
2585 case Hexagon::L4_loadrb_ap:
2586 case Hexagon::L2_loadrb_pr:
2587 case Hexagon::L2_loadrb_pbr:
2588 case Hexagon::L2_loadrb_pi:
2589 case Hexagon::L2_loadrb_pci:
2590 case Hexagon::L2_loadrb_pcr:
2591 case Hexagon::L2_loadbsw2_io:
2592 case Hexagon::L4_loadbsw2_ur:
2593 case Hexagon::L4_loadbsw2_ap:
2594 case Hexagon::L2_loadbsw2_pr:
2595 case Hexagon::L2_loadbsw2_pbr:
2596 case Hexagon::L2_loadbsw2_pi:
2597 case Hexagon::L2_loadbsw2_pci:
2598 case Hexagon::L2_loadbsw2_pcr:
2599 case Hexagon::L2_loadbsw4_io:
2600 case Hexagon::L4_loadbsw4_ur:
2601 case Hexagon::L4_loadbsw4_ap:
2602 case Hexagon::L2_loadbsw4_pr:
2603 case Hexagon::L2_loadbsw4_pbr:
2604 case Hexagon::L2_loadbsw4_pi:
2605 case Hexagon::L2_loadbsw4_pci:
2606 case Hexagon::L2_loadbsw4_pcr:
2607 case Hexagon::L4_loadrb_rr:
2608 case Hexagon::L2_ploadrbt_io:
2609 case Hexagon::L2_ploadrbt_pi:
2610 case Hexagon::L2_ploadrbf_io:
2611 case Hexagon::L2_ploadrbf_pi:
2612 case Hexagon::L2_ploadrbtnew_io:
2613 case Hexagon::L2_ploadrbfnew_io:
2614 case Hexagon::L4_ploadrbt_rr:
2615 case Hexagon::L4_ploadrbf_rr:
2616 case Hexagon::L4_ploadrbtnew_rr:
2617 case Hexagon::L4_ploadrbfnew_rr:
2618 case Hexagon::L2_ploadrbtnew_pi:
2619 case Hexagon::L2_ploadrbfnew_pi:
2620 case Hexagon::L4_ploadrbt_abs:
2621 case Hexagon::L4_ploadrbf_abs:
2622 case Hexagon::L4_ploadrbtnew_abs:
2623 case Hexagon::L4_ploadrbfnew_abs:
2624 case Hexagon::L2_loadrbgp:
2625
2626 case Hexagon::L2_loadrh_io:
2627 case Hexagon::L4_loadrh_ur:
2628 case Hexagon::L4_loadrh_ap:
2629 case Hexagon::L2_loadrh_pr:
2630 case Hexagon::L2_loadrh_pbr:
2631 case Hexagon::L2_loadrh_pi:
2632 case Hexagon::L2_loadrh_pci:
2633 case Hexagon::L2_loadrh_pcr:
2634 case Hexagon::L4_loadrh_rr:
2635 case Hexagon::L2_ploadrht_io:
2636 case Hexagon::L2_ploadrht_pi:
2637 case Hexagon::L2_ploadrhf_io:
2638 case Hexagon::L2_ploadrhf_pi:
2639 case Hexagon::L2_ploadrhtnew_io:
2640 case Hexagon::L2_ploadrhfnew_io:
2641 case Hexagon::L4_ploadrht_rr:
2642 case Hexagon::L4_ploadrhf_rr:
2643 case Hexagon::L4_ploadrhtnew_rr:
2644 case Hexagon::L4_ploadrhfnew_rr:
2645 case Hexagon::L2_ploadrhtnew_pi:
2646 case Hexagon::L2_ploadrhfnew_pi:
2647 case Hexagon::L4_ploadrht_abs:
2648 case Hexagon::L4_ploadrhf_abs:
2649 case Hexagon::L4_ploadrhtnew_abs:
2650 case Hexagon::L4_ploadrhfnew_abs:
2651 case Hexagon::L2_loadrhgp:
2652 return true;
2653 default:
2654 return false;
2655 }
2656}
2657
2662
2664 switch (MI.getOpcode()) {
2665 case Hexagon::STriw_pred:
2666 case Hexagon::LDriw_pred:
2667 return true;
2668 default:
2669 return false;
2670 }
2671}
2672
2674 if (.isBranch())
2675 return false;
2676
2677 for (auto &Op : MI.operands())
2678 if (Op.isGlobal() || Op.isSymbol())
2679 return true;
2680 return false;
2681}
2682
2683
2685 unsigned SchedClass = MI.getDesc().getSchedClass();
2686 return is_TC1(SchedClass);
2687}
2688
2690 unsigned SchedClass = MI.getDesc().getSchedClass();
2691 return is_TC2(SchedClass);
2692}
2693
2695 unsigned SchedClass = MI.getDesc().getSchedClass();
2697}
2698
2700 unsigned SchedClass = MI.getDesc().getSchedClass();
2701 return is_TC4x(SchedClass);
2702}
2703
2704
2708
2711 for (int I = 0; I < N; I++)
2713 return true;
2714 }
2716 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2719 return true;
2720 return false;
2721}
2722
2727
2728
2732 return false;
2734
2736
2737 case MVT::i8:
2738 case MVT::i16:
2739 case MVT::i32:
2740 case MVT::i64:
2741 case MVT::f32:
2742 case MVT::f64:
2743 case MVT::v2i16:
2744 case MVT::v2i32:
2745 case MVT::v4i8:
2746 case MVT::v4i16:
2747 case MVT::v8i8:
2749
2750 case MVT::v64i8:
2751 case MVT::v32i16:
2752 case MVT::v16i32:
2753 case MVT::v8i64:
2754 case MVT::v128i8:
2755 case MVT::v64i16:
2756 case MVT::v32i32:
2757 case MVT::v16i64:
2759 default:
2760 break;
2761 }
2762
2764}
2765
2768
2769
2770
2771
2772
2773
2774
2775
2776 switch (Opcode) {
2777 case Hexagon::PS_vstorerq_ai:
2778 case Hexagon::PS_vstorerv_ai:
2779 case Hexagon::PS_vstorerw_ai:
2780 case Hexagon::PS_vstorerw_nt_ai:
2781 case Hexagon::PS_vloadrq_ai:
2782 case Hexagon::PS_vloadrv_ai:
2783 case Hexagon::PS_vloadrw_ai:
2784 case Hexagon::PS_vloadrw_nt_ai:
2785 case Hexagon::V6_vL32b_ai:
2786 case Hexagon::V6_vS32b_ai:
2787 case Hexagon::V6_vS32b_pred_ai:
2788 case Hexagon::V6_vS32b_npred_ai:
2789 case Hexagon::V6_vS32b_qpred_ai:
2790 case Hexagon::V6_vS32b_nqpred_ai:
2791 case Hexagon::V6_vS32b_new_ai:
2792 case Hexagon::V6_vS32b_new_pred_ai:
2793 case Hexagon::V6_vS32b_new_npred_ai:
2794 case Hexagon::V6_vS32b_nt_pred_ai:
2795 case Hexagon::V6_vS32b_nt_npred_ai:
2796 case Hexagon::V6_vS32b_nt_new_ai:
2797 case Hexagon::V6_vS32b_nt_new_pred_ai:
2798 case Hexagon::V6_vS32b_nt_new_npred_ai:
2799 case Hexagon::V6_vS32b_nt_qpred_ai:
2800 case Hexagon::V6_vS32b_nt_nqpred_ai:
2801 case Hexagon::V6_vL32b_nt_ai:
2802 case Hexagon::V6_vS32b_nt_ai:
2803 case Hexagon::V6_vL32Ub_ai:
2804 case Hexagon::V6_vS32Ub_ai:
2805 case Hexagon::V6_vL32b_cur_ai:
2806 case Hexagon::V6_vL32b_tmp_ai:
2807 case Hexagon::V6_vL32b_pred_ai:
2808 case Hexagon::V6_vL32b_npred_ai:
2809 case Hexagon::V6_vL32b_cur_pred_ai:
2810 case Hexagon::V6_vL32b_cur_npred_ai:
2811 case Hexagon::V6_vL32b_tmp_pred_ai:
2812 case Hexagon::V6_vL32b_tmp_npred_ai:
2813 case Hexagon::V6_vL32b_nt_cur_ai:
2814 case Hexagon::V6_vL32b_nt_tmp_ai:
2815 case Hexagon::V6_vL32b_nt_pred_ai:
2816 case Hexagon::V6_vL32b_nt_npred_ai:
2817 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2818 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2819 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2820 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2821 case Hexagon::V6_vS32Ub_npred_ai:
2822 case Hexagon::V6_vgathermh_pseudo:
2823 case Hexagon::V6_vgather_vscatter_mh_pseudo:
2824 case Hexagon::V6_vgathermw_pseudo:
2825 case Hexagon::V6_vgathermhw_pseudo:
2826 case Hexagon::V6_vgathermhq_pseudo:
2827 case Hexagon::V6_vgathermwq_pseudo:
2828 case Hexagon::V6_vgathermhwq_pseudo: {
2829 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2831 if (Offset & (VectorSize-1))
2832 return false;
2834 }
2835
2836 case Hexagon::J2_loop0i:
2837 case Hexagon::J2_loop1i:
2839
2840 case Hexagon::S4_storeirb_io:
2841 case Hexagon::S4_storeirbt_io:
2842 case Hexagon::S4_storeirbf_io:
2844
2845 case Hexagon::S4_storeirh_io:
2846 case Hexagon::S4_storeirht_io:
2847 case Hexagon::S4_storeirhf_io:
2849
2850 case Hexagon::S4_storeiri_io:
2851 case Hexagon::S4_storeirit_io:
2852 case Hexagon::S4_storeirif_io:
2854
2855 case Hexagon::A4_cmpbeqi:
2857 case Hexagon::A4_cmpbgti:
2859 }
2860
2861 if (Extend)
2862 return true;
2863
2864 switch (Opcode) {
2865 case Hexagon::L2_loadri_io:
2866 case Hexagon::S2_storeri_io:
2869
2870 case Hexagon::L2_loadrd_io:
2871 case Hexagon::S2_storerd_io:
2874
2875 case Hexagon::L2_loadrh_io:
2876 case Hexagon::L2_loadruh_io:
2877 case Hexagon::S2_storerh_io:
2878 case Hexagon::S2_storerf_io:
2881
2882 case Hexagon::L2_loadrb_io:
2883 case Hexagon::L2_loadrub_io:
2884 case Hexagon::S2_storerb_io:
2887
2888 case Hexagon::A2_addi:
2891
2892 case Hexagon::L4_iadd_memopw_io:
2893 case Hexagon::L4_isub_memopw_io:
2894 case Hexagon::L4_add_memopw_io:
2895 case Hexagon::L4_sub_memopw_io:
2896 case Hexagon::L4_iand_memopw_io:
2897 case Hexagon::L4_ior_memopw_io:
2898 case Hexagon::L4_and_memopw_io:
2899 case Hexagon::L4_or_memopw_io:
2901
2902 case Hexagon::L4_iadd_memoph_io:
2903 case Hexagon::L4_isub_memoph_io:
2904 case Hexagon::L4_add_memoph_io:
2905 case Hexagon::L4_sub_memoph_io:
2906 case Hexagon::L4_iand_memoph_io:
2907 case Hexagon::L4_ior_memoph_io:
2908 case Hexagon::L4_and_memoph_io:
2909 case Hexagon::L4_or_memoph_io:
2911
2912 case Hexagon::L4_iadd_memopb_io:
2913 case Hexagon::L4_isub_memopb_io:
2914 case Hexagon::L4_add_memopb_io:
2915 case Hexagon::L4_sub_memopb_io:
2916 case Hexagon::L4_iand_memopb_io:
2917 case Hexagon::L4_ior_memopb_io:
2918 case Hexagon::L4_and_memopb_io:
2919 case Hexagon::L4_or_memopb_io:
2921
2922
2923
2924 case Hexagon::STriw_pred:
2925 case Hexagon::LDriw_pred:
2926 case Hexagon::STriw_ctr:
2927 case Hexagon::LDriw_ctr:
2928 return true;
2929
2930 case Hexagon::PS_fi:
2931 case Hexagon::PS_fia:
2932 case Hexagon::INLINEASM:
2933 return true;
2934
2935 case Hexagon::L2_ploadrbt_io:
2936 case Hexagon::L2_ploadrbf_io:
2937 case Hexagon::L2_ploadrubt_io:
2938 case Hexagon::L2_ploadrubf_io:
2939 case Hexagon::S2_pstorerbt_io:
2940 case Hexagon::S2_pstorerbf_io:
2942
2943 case Hexagon::L2_ploadrht_io:
2944 case Hexagon::L2_ploadrhf_io:
2945 case Hexagon::L2_ploadruht_io:
2946 case Hexagon::L2_ploadruhf_io:
2947 case Hexagon::S2_pstorerht_io:
2948 case Hexagon::S2_pstorerhf_io:
2950
2951 case Hexagon::L2_ploadrit_io:
2952 case Hexagon::L2_ploadrif_io:
2953 case Hexagon::S2_pstorerit_io:
2954 case Hexagon::S2_pstorerif_io:
2956
2957 case Hexagon::L2_ploadrdt_io:
2958 case Hexagon::L2_ploadrdf_io:
2959 case Hexagon::S2_pstorerdt_io:
2960 case Hexagon::S2_pstorerdf_io:
2962
2963 case Hexagon::L2_loadbsw2_io:
2964 case Hexagon::L2_loadbzw2_io:
2966
2967 case Hexagon::L2_loadbsw4_io:
2968 case Hexagon::L2_loadbzw4_io:
2970 }
2971
2972 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2973 << ")\n";
2974 llvm_unreachable("No offset range is defined for this opcode. "
2975 "Please define it in the above switch statement!");
2976}
2977
2981
2989
2993 return true;
2994
2996 return true;
2997
2999 return true;
3000
3001 return false;
3002}
3003
3005 switch (MI.getOpcode()) {
3006
3007 case Hexagon::L2_loadrub_io:
3008 case Hexagon::L4_loadrub_ur:
3009 case Hexagon::L4_loadrub_ap:
3010 case Hexagon::L2_loadrub_pr:
3011 case Hexagon::L2_loadrub_pbr:
3012 case Hexagon::L2_loadrub_pi:
3013 case Hexagon::L2_loadrub_pci:
3014 case Hexagon::L2_loadrub_pcr:
3015 case Hexagon::L2_loadbzw2_io:
3016 case Hexagon::L4_loadbzw2_ur:
3017 case Hexagon::L4_loadbzw2_ap:
3018 case Hexagon::L2_loadbzw2_pr:
3019 case Hexagon::L2_loadbzw2_pbr:
3020 case Hexagon::L2_loadbzw2_pi:
3021 case Hexagon::L2_loadbzw2_pci:
3022 case Hexagon::L2_loadbzw2_pcr:
3023 case Hexagon::L2_loadbzw4_io:
3024 case Hexagon::L4_loadbzw4_ur:
3025 case Hexagon::L4_loadbzw4_ap:
3026 case Hexagon::L2_loadbzw4_pr:
3027 case Hexagon::L2_loadbzw4_pbr:
3028 case Hexagon::L2_loadbzw4_pi:
3029 case Hexagon::L2_loadbzw4_pci:
3030 case Hexagon::L2_loadbzw4_pcr:
3031 case Hexagon::L4_loadrub_rr:
3032 case Hexagon::L2_ploadrubt_io:
3033 case Hexagon::L2_ploadrubt_pi:
3034 case Hexagon::L2_ploadrubf_io:
3035 case Hexagon::L2_ploadrubf_pi:
3036 case Hexagon::L2_ploadrubtnew_io:
3037 case Hexagon::L2_ploadrubfnew_io:
3038 case Hexagon::L4_ploadrubt_rr:
3039 case Hexagon::L4_ploadrubf_rr:
3040 case Hexagon::L4_ploadrubtnew_rr:
3041 case Hexagon::L4_ploadrubfnew_rr:
3042 case Hexagon::L2_ploadrubtnew_pi:
3043 case Hexagon::L2_ploadrubfnew_pi:
3044 case Hexagon::L4_ploadrubt_abs:
3045 case Hexagon::L4_ploadrubf_abs:
3046 case Hexagon::L4_ploadrubtnew_abs:
3047 case Hexagon::L4_ploadrubfnew_abs:
3048 case Hexagon::L2_loadrubgp:
3049
3050 case Hexagon::L2_loadruh_io:
3051 case Hexagon::L4_loadruh_ur:
3052 case Hexagon::L4_loadruh_ap:
3053 case Hexagon::L2_loadruh_pr:
3054 case Hexagon::L2_loadruh_pbr:
3055 case Hexagon::L2_loadruh_pi:
3056 case Hexagon::L2_loadruh_pci:
3057 case Hexagon::L2_loadruh_pcr:
3058 case Hexagon::L4_loadruh_rr:
3059 case Hexagon::L2_ploadruht_io:
3060 case Hexagon::L2_ploadruht_pi:
3061 case Hexagon::L2_ploadruhf_io:
3062 case Hexagon::L2_ploadruhf_pi:
3063 case Hexagon::L2_ploadruhtnew_io:
3064 case Hexagon::L2_ploadruhfnew_io:
3065 case Hexagon::L4_ploadruht_rr:
3066 case Hexagon::L4_ploadruhf_rr:
3067 case Hexagon::L4_ploadruhtnew_rr:
3068 case Hexagon::L4_ploadruhfnew_rr:
3069 case Hexagon::L2_ploadruhtnew_pi:
3070 case Hexagon::L2_ploadruhfnew_pi:
3071 case Hexagon::L4_ploadruht_abs:
3072 case Hexagon::L4_ploadruhf_abs:
3073 case Hexagon::L4_ploadruhtnew_abs:
3074 case Hexagon::L4_ploadruhfnew_abs:
3075 case Hexagon::L2_loadruhgp:
3076 return true;
3077 default:
3078 return false;
3079 }
3080}
3081
3082
3087 return true;
3088 return false;
3089}
3090
3091
3096 OffsetIsScalable = false;
3098 if (!BaseOp || !BaseOp->isReg())
3099 return false;
3101 return true;
3102}
3103
3104
3107 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3109 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3110 return true;
3111 }
3113 return false;
3115
3116
3119 if (!Stored.isReg())
3120 return false;
3121 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3123 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3124 return true;
3125 }
3126 }
3127 return false;
3128}
3129
3132 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3133}
3134
3137 if (I.isEHLabel())
3138 return true;
3139 return false;
3140}
3141
3142
3143
3145 short NonExtOpcode;
3146
3147
3148 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3149 return true;
3150
3151 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3152
3153
3156
3157
3158 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3159 break;
3161
3162
3163
3164 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3165 break;
3167 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3168 break;
3169 default:
3170 return false;
3171 }
3172 if (NonExtOpcode < 0)
3173 return false;
3174 return true;
3175 }
3176 return false;
3177}
3178
3180 return Hexagon::getRealHWInstr(MI.getOpcode(),
3181 Hexagon::InstrType_Pseudo) >= 0;
3182}
3183
3185 const {
3187 while (I != E) {
3188 if (I->isBarrier())
3189 return true;
3190 ++I;
3191 }
3192 return false;
3193}
3194
3195
3197 const uint64_t F = MI.getDesc().TSFlags;
3199 Subtarget.hasV60Ops();
3200}
3201
3202
3204 if (MI.mayStore() && !Subtarget.useNewValueStores())
3205 return false;
3206
3207 const uint64_t F = MI.getDesc().TSFlags;
3209}
3210
3213
3215 return false;
3216
3217
3219 return false;
3220
3221
3222
3224 return false;
3225
3226 return true;
3227}
3228
3231
3233 return false;
3234
3237
3238 if (!MII->isBundle())
3240
3241 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3244 return true;
3245 }
3246 return false;
3247}
3248
3252
3253 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3254 return false;
3255 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3256 return false;
3257 }
3258
3259
3260
3261 switch (MI.getOpcode()) {
3262 case Hexagon::A4_addp_c:
3263 case Hexagon::A4_subp_c:
3264 case Hexagon::A4_tlbmatch:
3265 case Hexagon::A5_ACS:
3266 case Hexagon::F2_sfinvsqrta:
3267 case Hexagon::F2_sfrecipa:
3268 case Hexagon::J2_endloop0:
3269 case Hexagon::J2_endloop01:
3270 case Hexagon::J2_ploop1si:
3271 case Hexagon::J2_ploop1sr:
3272 case Hexagon::J2_ploop2si:
3273 case Hexagon::J2_ploop2sr:
3274 case Hexagon::J2_ploop3si:
3275 case Hexagon::J2_ploop3sr:
3276 case Hexagon::S2_cabacdecbin:
3277 case Hexagon::S2_storew_locked:
3278 case Hexagon::S4_stored_locked:
3279 return false;
3280 }
3281 return true;
3282}
3283
3285 return Opcode == Hexagon::J2_jumpt ||
3286 Opcode == Hexagon::J2_jumptpt ||
3287 Opcode == Hexagon::J2_jumpf ||
3288 Opcode == Hexagon::J2_jumpfpt ||
3289 Opcode == Hexagon::J2_jumptnew ||
3290 Opcode == Hexagon::J2_jumpfnew ||
3291 Opcode == Hexagon::J2_jumptnewpt ||
3292 Opcode == Hexagon::J2_jumpfnewpt;
3293}
3294
3300
3305
3306
3307
3308
3309
3313
3317 return nullptr;
3318
3320
3321 unsigned BasePos = 0, OffsetPos = 0;
3323 return nullptr;
3324
3325
3326
3329 } else {
3332 return nullptr;
3334 }
3335
3338 return nullptr;
3340}
3341
3342
3344 unsigned &BasePos, unsigned &OffsetPos) const {
3346 return false;
3347
3348
3350 BasePos = 0;
3351 OffsetPos = 1;
3352 } else if (MI.mayStore()) {
3353 BasePos = 0;
3354 OffsetPos = 1;
3355 } else if (MI.mayLoad()) {
3356 BasePos = 1;
3357 OffsetPos = 2;
3358 } else
3359 return false;
3360
3362 BasePos++;
3363 OffsetPos++;
3364 }
3366 BasePos++;
3367 OffsetPos++;
3368 }
3369
3370 if (.getOperand(BasePos).isReg() ||
.getOperand(OffsetPos).isImm())
3371 return false;
3372
3373 return true;
3374}
3375
3376
3377
3378
3379
3383
3385 if (I == MBB.instr_begin())
3386 return Jumpers;
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400 do {
3401 --I;
3402 if (I->isEHLabel())
3403 return Jumpers;
3404 } while (I != MBB.instr_begin());
3405
3407 --I;
3408
3409 while (I->isDebugInstr()) {
3410 if (I == MBB.instr_begin())
3411 return Jumpers;
3412 --I;
3413 }
3414 if (!isUnpredicatedTerminator(*I))
3415 return Jumpers;
3416
3417
3421
3422 do {
3423 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
3424 if (!SecondLastInst) {
3425 SecondLastInst = &*I;
3426 Jumpers.push_back(SecondLastInst);
3427 } else
3428 return Jumpers;
3429 }
3430 if (I == MBB.instr_begin())
3431 break;
3432 --I;
3433 } while (true);
3434 return Jumpers;
3435}
3436
3437
3442
3443
3444
3447 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3448
3449 switch (MI.getOpcode()) {
3450 default:
3452
3453
3454
3455
3456
3457
3458 case Hexagon::C2_cmpeq:
3459 case Hexagon::C2_cmpgt:
3460 case Hexagon::C2_cmpgtu:
3461 DstReg = MI.getOperand(0).getReg();
3462 Src1Reg = MI.getOperand(1).getReg();
3463 Src2Reg = MI.getOperand(2).getReg();
3464 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3465 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3468 break;
3469 case Hexagon::C2_cmpeqi:
3470 case Hexagon::C2_cmpgti:
3471 case Hexagon::C2_cmpgtui:
3472
3473 DstReg = MI.getOperand(0).getReg();
3474 SrcReg = MI.getOperand(1).getReg();
3475 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3476 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3478 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3479 (MI.getOperand(2).getImm() == -1)))
3481 break;
3482 case Hexagon::A2_tfr:
3483
3484 DstReg = MI.getOperand(0).getReg();
3485 SrcReg = MI.getOperand(1).getReg();
3488 break;
3489 case Hexagon::A2_tfrsi:
3490
3491
3492
3493 DstReg = MI.getOperand(0).getReg();
3496 break;
3497 case Hexagon::S2_tstbit_i:
3498 DstReg = MI.getOperand(0).getReg();
3499 Src1Reg = MI.getOperand(1).getReg();
3500 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3501 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3502 MI.getOperand(2).isImm() &&
3505 break;
3506
3507
3508
3509
3510 case Hexagon::J2_jumptnew:
3511 case Hexagon::J2_jumpfnew:
3512 case Hexagon::J2_jumptnewpt:
3513 case Hexagon::J2_jumpfnewpt:
3514 Src1Reg = MI.getOperand(0).getReg();
3515 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3516 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3518 break;
3519
3520
3521
3522
3523 case Hexagon::J2_jump:
3524 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3525 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3527 }
3528
3530}
3531
3532
3537 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3538 (GB.getOpcode() != Hexagon::J2_jumptnew))
3539 return -1u;
3541 if (!GB.readsRegister(DestReg, nullptr))
3542 return -1u;
3543 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3544 return -1u;
3545
3547 if (!CmpOp.isImm())
3548 return -1u;
3549 int V = CmpOp.getImm();
3550 if (V == -1)
3551 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3552 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3554 return -1u;
3555 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3556 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3557}
3558
3559
3561 bool ForBigCore) const {
3562
3563
3564
3565
3566
3567
3568
3569 static const std::map<unsigned, unsigned> DupMap = {
3570 {Hexagon::A2_add, Hexagon::dup_A2_add},
3571 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3572 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3573 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3574 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3575 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3576 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3577 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3578 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3579 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3580 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3581 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3582 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3583 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3584 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3585 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3586 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3587 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3588 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3589 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3590 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3591 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3592 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3593 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3594 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3595 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3596 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3597 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3598 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3599 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3600 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3601 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3602 };
3603 unsigned OpNum = MI.getOpcode();
3604
3605 if (ForBigCore) {
3606 auto Iter = DupMap.find(OpNum);
3607 if (Iter != DupMap.end())
3608 return Iter->second;
3609 } else {
3610 for (const auto &Iter : DupMap)
3611 if (Iter.second == OpNum)
3612 return Iter.first;
3613 }
3614 return -1;
3615}
3616
3618 enum Hexagon::PredSense inPredSense;
3619 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3620 Hexagon::PredSense_true;
3621 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3622 if (CondOpcode >= 0)
3623 return CondOpcode;
3624
3626}
3627
3628
3630 switch (MI.getOpcode()) {
3632 case Hexagon::V6_vL32b_pi:
3633 return Hexagon::V6_vL32b_cur_pi;
3634 case Hexagon::V6_vL32b_ai:
3635 return Hexagon::V6_vL32b_cur_ai;
3636 case Hexagon::V6_vL32b_nt_pi:
3637 return Hexagon::V6_vL32b_nt_cur_pi;
3638 case Hexagon::V6_vL32b_nt_ai:
3639 return Hexagon::V6_vL32b_nt_cur_ai;
3640 case Hexagon::V6_vL32b_ppu:
3641 return Hexagon::V6_vL32b_cur_ppu;
3642 case Hexagon::V6_vL32b_nt_ppu:
3643 return Hexagon::V6_vL32b_nt_cur_ppu;
3644 }
3645 return 0;
3646}
3647
3648
3650 switch (MI.getOpcode()) {
3652 case Hexagon::V6_vL32b_cur_pi:
3653 return Hexagon::V6_vL32b_pi;
3654 case Hexagon::V6_vL32b_cur_ai:
3655 return Hexagon::V6_vL32b_ai;
3656 case Hexagon::V6_vL32b_nt_cur_pi:
3657 return Hexagon::V6_vL32b_nt_pi;
3658 case Hexagon::V6_vL32b_nt_cur_ai:
3659 return Hexagon::V6_vL32b_nt_ai;
3660 case Hexagon::V6_vL32b_cur_ppu:
3661 return Hexagon::V6_vL32b_ppu;
3662 case Hexagon::V6_vL32b_nt_cur_ppu:
3663 return Hexagon::V6_vL32b_nt_ppu;
3664 }
3665 return 0;
3666}
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3751 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3752 if (NVOpcode >= 0)
3753 return NVOpcode;
3754
3755 switch (MI.getOpcode()) {
3756 default:
3758 std::to_string(MI.getOpcode()));
3759 case Hexagon::S4_storerb_ur:
3760 return Hexagon::S4_storerbnew_ur;
3761
3762 case Hexagon::S2_storerb_pci:
3763 return Hexagon::S2_storerb_pci;
3764
3765 case Hexagon::S2_storeri_pci:
3766 return Hexagon::S2_storeri_pci;
3767
3768 case Hexagon::S2_storerh_pci:
3769 return Hexagon::S2_storerh_pci;
3770
3771 case Hexagon::S2_storerd_pci:
3772 return Hexagon::S2_storerd_pci;
3773
3774 case Hexagon::S2_storerf_pci:
3775 return Hexagon::S2_storerf_pci;
3776
3777 case Hexagon::V6_vS32b_ai:
3778 return Hexagon::V6_vS32b_new_ai;
3779
3780 case Hexagon::V6_vS32b_pi:
3781 return Hexagon::V6_vS32b_new_pi;
3782 }
3783 return 0;
3784}
3785
3786
3787
3788
3789
3790
3793
3796 bool Taken = false;
3798
3801 if (MBPI)
3804 };
3805
3806 if (BrTarget.isMBB()) {
3808 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3809 } else {
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819 assert(MI.isConditionalBranch());
3821 bool SawCond = false, Bad = false;
3823 if (.isBranch())
3824 continue;
3825 if (I.isConditionalBranch()) {
3826 SawCond = true;
3828 Bad = true;
3829 break;
3830 }
3831 }
3832 if (I.isUnconditionalBranch() && !SawCond) {
3833 Bad = true;
3834 break;
3835 }
3836 }
3837 if (!Bad) {
3840 if (NextIt == B.instr_end()) {
3841
3843 if (.isLayoutSuccessor(SB))
3844 continue;
3845 Taken = getEdgeProbability(Src, SB) < OneHalf;
3846 break;
3847 }
3848 } else {
3849 assert(NextIt->isUnconditionalBranch());
3850
3853 if (.isMBB())
3854 continue;
3856 break;
3857 }
3858 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3859 }
3860 }
3861 }
3862
3863
3864
3865 switch (MI.getOpcode()) {
3866 case Hexagon::J2_jumpt:
3867 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3868 case Hexagon::J2_jumpf:
3869 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3870
3871 default:
3873 }
3874}
3875
3876
3879 switch (MI.getOpcode()) {
3880
3881 case Hexagon::J2_jumpt:
3882 case Hexagon::J2_jumpf:
3884 }
3885
3886 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3887 if (NewOpcode >= 0)
3888 return NewOpcode;
3889 return 0;
3890}
3891
3893 int NewOp = MI.getOpcode();
3895 NewOp = Hexagon::getPredOldOpcode(NewOp);
3896
3897
3898
3899 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3900 switch (NewOp) {
3901 case Hexagon::J2_jumptpt:
3902 NewOp = Hexagon::J2_jumpt;
3903 break;
3904 case Hexagon::J2_jumpfpt:
3905 NewOp = Hexagon::J2_jumpf;
3906 break;
3907 case Hexagon::J2_jumprtpt:
3908 NewOp = Hexagon::J2_jumprt;
3909 break;
3910 case Hexagon::J2_jumprfpt:
3911 NewOp = Hexagon::J2_jumprf;
3912 break;
3913 }
3914 }
3915 assert(NewOp >= 0 &&
3916 "Couldn't change predicate new instruction to its old form.");
3917 }
3918
3919 if (isNewValueStore(NewOp)) {
3920 NewOp = Hexagon::getNonNVStore(NewOp);
3921 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3922 }
3923
3924 if (Subtarget.hasV60Ops())
3925 return NewOp;
3926
3927
3928 switch (NewOp) {
3929 case Hexagon::J2_jumpfpt:
3930 return Hexagon::J2_jumpf;
3931 case Hexagon::J2_jumptpt:
3932 return Hexagon::J2_jumpt;
3933 case Hexagon::J2_jumprfpt:
3934 return Hexagon::J2_jumprf;
3935 case Hexagon::J2_jumprtpt:
3936 return Hexagon::J2_jumprt;
3937 }
3938 return NewOp;
3939}
3940
3941
3942
3945 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3947
3948 switch (MI.getOpcode()) {
3949 default:
3951
3952
3953
3954
3955
3956 case Hexagon::L2_loadri_io:
3957 case Hexagon::dup_L2_loadri_io:
3958 DstReg = MI.getOperand(0).getReg();
3959 SrcReg = MI.getOperand(1).getReg();
3960
3961
3963 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3965 MI.getOperand(2).isImm() &&
3968
3970 (MI.getOperand(2).isImm() &&
3973 }
3974 break;
3975 case Hexagon::L2_loadrub_io:
3976 case Hexagon::dup_L2_loadrub_io:
3977
3978 DstReg = MI.getOperand(0).getReg();
3979 SrcReg = MI.getOperand(1).getReg();
3981 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3983 break;
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994 case Hexagon::L2_loadrh_io:
3995 case Hexagon::L2_loadruh_io:
3996 case Hexagon::dup_L2_loadrh_io:
3997 case Hexagon::dup_L2_loadruh_io:
3998
3999 DstReg = MI.getOperand(0).getReg();
4000 SrcReg = MI.getOperand(1).getReg();
4002 MI.getOperand(2).isImm() &&
4005 break;
4006 case Hexagon::L2_loadrb_io:
4007 case Hexagon::dup_L2_loadrb_io:
4008
4009 DstReg = MI.getOperand(0).getReg();
4010 SrcReg = MI.getOperand(1).getReg();
4012 MI.getOperand(2).isImm() &&
4015 break;
4016 case Hexagon::L2_loadrd_io:
4017 case Hexagon::dup_L2_loadrd_io:
4018
4019 DstReg = MI.getOperand(0).getReg();
4020 SrcReg = MI.getOperand(1).getReg();
4022 Hexagon::IntRegsRegClass.contains(SrcReg) &&
4024 MI.getOperand(2).isImm() &&
4027 break;
4028
4029
4030 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4031 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4032 case Hexagon::L4_return:
4033 case Hexagon::L2_deallocframe:
4034 case Hexagon::dup_L2_deallocframe:
4036 case Hexagon::EH_RETURN_JMPR:
4037 case Hexagon::PS_jmpret:
4038 case Hexagon::SL2_jumpr31:
4039
4040
4041 DstReg = MI.getOperand(0).getReg();
4042 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4044 break;
4045 case Hexagon::PS_jmprett:
4046 case Hexagon::PS_jmpretf:
4047 case Hexagon::PS_jmprettnewpt:
4048 case Hexagon::PS_jmpretfnewpt:
4049 case Hexagon::PS_jmprettnew:
4050 case Hexagon::PS_jmpretfnew:
4051 case Hexagon::SL2_jumpr31_t:
4052 case Hexagon::SL2_jumpr31_f:
4053 case Hexagon::SL2_jumpr31_tnew:
4054 case Hexagon::SL2_jumpr31_fnew:
4055 DstReg = MI.getOperand(1).getReg();
4056 SrcReg = MI.getOperand(0).getReg();
4057
4058 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4059 (Hexagon::P0 == SrcReg)) &&
4060 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4062 break;
4063 case Hexagon::L4_return_t:
4064 case Hexagon::L4_return_f:
4065 case Hexagon::L4_return_tnew_pnt:
4066 case Hexagon::L4_return_fnew_pnt:
4067 case Hexagon::L4_return_tnew_pt:
4068 case Hexagon::L4_return_fnew_pt:
4069
4070 SrcReg = MI.getOperand(0).getReg();
4071 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4073 break;
4074
4075
4076
4077
4078
4079 case Hexagon::S2_storeri_io:
4080 case Hexagon::dup_S2_storeri_io:
4081
4082
4083 Src1Reg = MI.getOperand(0).getReg();
4084 Src2Reg = MI.getOperand(2).getReg();
4085 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4090
4092 MI.getOperand(1).isImm() &&
4095 break;
4096 case Hexagon::S2_storerb_io:
4097 case Hexagon::dup_S2_storerb_io:
4098
4099 Src1Reg = MI.getOperand(0).getReg();
4100 Src2Reg = MI.getOperand(2).getReg();
4102 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4104 break;
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114 case Hexagon::S2_storerh_io:
4115 case Hexagon::dup_S2_storerh_io:
4116
4117 Src1Reg = MI.getOperand(0).getReg();
4118 Src2Reg = MI.getOperand(2).getReg();
4120 MI.getOperand(1).isImm() &&
4123 break;
4124 case Hexagon::S2_storerd_io:
4125 case Hexagon::dup_S2_storerd_io:
4126
4127 Src1Reg = MI.getOperand(0).getReg();
4128 Src2Reg = MI.getOperand(2).getReg();
4130 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4134 break;
4135 case Hexagon::S4_storeiri_io:
4136 case Hexagon::dup_S4_storeiri_io:
4137
4138 Src1Reg = MI.getOperand(0).getReg();
4141 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4143 break;
4144 case Hexagon::S4_storeirb_io:
4145 case Hexagon::dup_S4_storeirb_io:
4146
4147 Src1Reg = MI.getOperand(0).getReg();
4149 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4150 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4152 break;
4153 case Hexagon::S2_allocframe:
4154 case Hexagon::dup_S2_allocframe:
4155 if (MI.getOperand(2).isImm() &&
4158 break;
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177 case Hexagon::A2_addi:
4178 case Hexagon::dup_A2_addi:
4179 DstReg = MI.getOperand(0).getReg();
4180 SrcReg = MI.getOperand(1).getReg();
4182
4183 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4187
4188 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4189 isInt<7>(MI.getOperand(2).getImm()))
4191
4192
4194 ((MI.getOperand(2).getImm() == 1) ||
4195 (MI.getOperand(2).getImm() == -1)))
4197 }
4198 break;
4199 case Hexagon::A2_add:
4200 case Hexagon::dup_A2_add:
4201
4202 DstReg = MI.getOperand(0).getReg();
4203 Src1Reg = MI.getOperand(1).getReg();
4204 Src2Reg = MI.getOperand(2).getReg();
4208 break;
4209 case Hexagon::A2_andir:
4210 case Hexagon::dup_A2_andir:
4211
4212
4213
4214 DstReg = MI.getOperand(0).getReg();
4215 SrcReg = MI.getOperand(1).getReg();
4217 MI.getOperand(2).isImm() &&
4218 ((MI.getOperand(2).getImm() == 1) ||
4219 (MI.getOperand(2).getImm() == 255)))
4221 break;
4222 case Hexagon::A2_tfr:
4223 case Hexagon::dup_A2_tfr:
4224
4225 DstReg = MI.getOperand(0).getReg();
4226 SrcReg = MI.getOperand(1).getReg();
4229 break;
4230 case Hexagon::A2_tfrsi:
4231 case Hexagon::dup_A2_tfrsi:
4232
4233
4234
4235
4236 DstReg = MI.getOperand(0).getReg();
4239 break;
4240 case Hexagon::C2_cmoveit:
4241 case Hexagon::C2_cmovenewit:
4242 case Hexagon::C2_cmoveif:
4243 case Hexagon::C2_cmovenewif:
4244 case Hexagon::dup_C2_cmoveit:
4245 case Hexagon::dup_C2_cmovenewit:
4246 case Hexagon::dup_C2_cmoveif:
4247 case Hexagon::dup_C2_cmovenewif:
4248
4249
4250
4251 DstReg = MI.getOperand(0).getReg();
4252 SrcReg = MI.getOperand(1).getReg();
4254 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4255 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4257 break;
4258 case Hexagon::C2_cmpeqi:
4259 case Hexagon::dup_C2_cmpeqi:
4260
4261 DstReg = MI.getOperand(0).getReg();
4262 SrcReg = MI.getOperand(1).getReg();
4263 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4265 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4267 break;
4268 case Hexagon::A2_combineii:
4269 case Hexagon::A4_combineii:
4270 case Hexagon::dup_A2_combineii:
4271 case Hexagon::dup_A4_combineii:
4272
4273 DstReg = MI.getOperand(0).getReg();
4275 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4276 (MI.getOperand(1).isGlobal() &&
4277 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4278 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4279 (MI.getOperand(2).isGlobal() &&
4280 isUInt<2>(MI.getOperand(2).getOffset()))))
4282 break;
4283 case Hexagon::A4_combineri:
4284 case Hexagon::dup_A4_combineri:
4285
4286
4287 DstReg = MI.getOperand(0).getReg();
4288 SrcReg = MI.getOperand(1).getReg();
4290 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4291 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4293 break;
4294 case Hexagon::A4_combineir:
4295 case Hexagon::dup_A4_combineir:
4296
4297 DstReg = MI.getOperand(0).getReg();
4298 SrcReg = MI.getOperand(2).getReg();
4300 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4301 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4303 break;
4304 case Hexagon::A2_sxtb:
4305 case Hexagon::A2_sxth:
4306 case Hexagon::A2_zxtb:
4307 case Hexagon::A2_zxth:
4308 case Hexagon::dup_A2_sxtb:
4309 case Hexagon::dup_A2_sxth:
4310 case Hexagon::dup_A2_zxtb:
4311 case Hexagon::dup_A2_zxth:
4312
4313 DstReg = MI.getOperand(0).getReg();
4314 SrcReg = MI.getOperand(1).getReg();
4317 break;
4318 }
4319
4321}
4322
4324 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4325}
4326
4329
4330
4331 if (!ItinData)
4333
4334 if (MI.isTransient())
4335 return 0;
4337}
4338
4339
4340
4341
4342
4343
4344
4345
4346
4349 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4351
4352
4354
4358 int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false);
4359 if (Idx != -1) {
4360 DefIdx = Idx;
4361 break;
4362 }
4363 }
4364 }
4365
4369 int Idx = UseMI.findRegisterUseOperandIdx(SR, &HRI, false);
4370 if (Idx != -1) {
4371 UseIdx = Idx;
4372 break;
4373 }
4374 }
4375 }
4376 }
4377
4379 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4381
4382
4383
4386}
4387
4388
4389
4390
4393 if (Cond.empty())
4394 return false;
4397 return true;
4398}
4399
4401 int InvPredOpcode;
4403 : Hexagon::getTruePredOpcode(Opc);
4404 if (InvPredOpcode >= 0)
4405 return InvPredOpcode;
4406
4408}
4409
4410
4412 const uint64_t F = MI.getDesc().TSFlags;
4417
4418 if (isSigned)
4419 return ~(-1U << (bits - 1));
4420 else
4421 return ~(-1U << bits);
4422}
4423
4424
4426 switch (MI.getOpcode()) {
4427 case Hexagon::L2_loadrbgp:
4428 case Hexagon::L2_loadrdgp:
4429 case Hexagon::L2_loadrhgp:
4430 case Hexagon::L2_loadrigp:
4431 case Hexagon::L2_loadrubgp:
4432 case Hexagon::L2_loadruhgp:
4433 case Hexagon::S2_storerbgp:
4434 case Hexagon::S2_storerbnewgp:
4435 case Hexagon::S2_storerhgp:
4436 case Hexagon::S2_storerhnewgp:
4437 case Hexagon::S2_storerigp:
4438 case Hexagon::S2_storerinewgp:
4439 case Hexagon::S2_storerdgp:
4440 case Hexagon::S2_storerfgp:
4441 return true;
4442 }
4443 const uint64_t F = MI.getDesc().TSFlags;
4444 unsigned addrMode =
4446
4447
4451}
4452
4454
4455
4456
4457
4458 if (MI.getOpcode() == Hexagon::A4_ext)
4459 return false;
4460
4463}
4464
4470
4472 bool ToBigInstrs) const {
4473 int Opcode = -1;
4474 if (ToBigInstrs) {
4475
4477
4479 } else
4481
4482
4483 if (Opcode >= 0)
4484 MII->setDesc(get(Opcode));
4485}
4486
4487
4488
4490 bool ToBigInstrs) const {
4491 for (auto &MB : MF)
4493 End = MB.instr_end();
4494 Instr != End; ++Instr)
4496}
4497
4498
4502 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4504 ++MII;
4505 }
4506}
4507
4510
4511 const uint64_t F = MI.getDesc().TSFlags;
4512 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4513 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4514 if (Size != 0)
4515 return Size;
4516
4517 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4519
4520
4522 switch (S) {
4524 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4525 default:
4527 }
4528}
4529
4530
4532 const uint64_t F = MI.getDesc().TSFlags;
4537
4538 if (isSigned)
4539 return -1U << (bits - 1);
4540 else
4541 return 0;
4542}
4543
4544
4546
4547
4548 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4549 if (NonExtOpcode >= 0)
4550 return NonExtOpcode;
4551
4552 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4553
4556 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4558 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4560 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4561
4562 default:
4563 return -1;
4564 }
4565 }
4566 return -1;
4567}
4568
4570 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4571 if (Cond.empty())
4572 return false;
4575 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4576 return false;
4577 }
4578 PredReg = Cond[1].getReg();
4579 PredRegPos = 1;
4580
4581 PredRegFlags = 0;
4582 if (Cond[1].isImplicit())
4586 return true;
4587}
4588
4590 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4591}
4592
4594 return Hexagon::getRegForm(MI.getOpcode());
4595}
4596
4597
4598
4599
4600
4602 if (MI.isDebugInstr() || MI.isPosition())
4603 return 0;
4604
4605 unsigned Size = MI.getDesc().getSize();
4607
4608
4610
4613
4614
4619
4620
4621 unsigned NumDefs = 0;
4622 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4623 ++NumDefs)
4624 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4625
4626 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4627
4628 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4630 }
4631
4632 return Size;
4633}
4634
4639
4642 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4643
4645}
4646
4647
4651
4654 assert(BundleHead->isBundle() && "Not a bundle header");
4656
4658}
4659
4660
4661
4664 "Instruction must be extendable");
4665
4668
4670 "Branch with unknown extendable field type");
4671
4673}
4674
4677 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4679 MI.dump(););
4682 int TargetPos = MI.getNumOperands() - 1;
4683
4684
4685 while ((TargetPos > -1) && .getOperand(TargetPos).isMBB())
4686 --TargetPos;
4687 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4688 MI.getOperand(TargetPos).setMBB(NewTarget);
4691 }
4692 MI.setDesc(get(NewOpcode));
4693 return true;
4694}
4695
4697
4703
4704 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4705 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4711 }
4712
4713}
4714
4715
4716
4717
4719 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4721 return true;
4722}
4723
4724
4726 int PredRevOpcode = -1;
4728 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4729 else
4730 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4731 assert(PredRevOpcode > 0);
4732 return PredRevOpcode;
4733}
4734
4735
4737 const {
4738 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4739}
4740
4743 assert(MIB->isBundle());
4745 if (Operand.isImm())
4746 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4747 else
4749}
4750
4754 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4755}
4756
4758 return (MI->getOpcode() == Hexagon::V6_vmpy_qf16_hf ||
4759 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4760 MI->getOpcode() == Hexagon::V6_vmpy_qf32_hf ||
4761 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4762 MI->getOpcode() == Hexagon::V6_vmpy_qf32_sf ||
4763 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4764 MI->getOpcode() == Hexagon::V6_vmpy_qf16 ||
4765 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4766 MI->getOpcode() == Hexagon::V6_vmpy_qf32_qf16 ||
4767 MI->getOpcode() == Hexagon::V6_vmpy_qf32);
4768}
4769
4770
4772 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4773}
4774
4776 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4777}
4778
4780 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4781}
4782
4784 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4785}
4786
4788 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4789}
4790
4792 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4793}
4794
4796 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4797}
4798
4800 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4801}
4802
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool mayAlias(MachineInstr &MIa, SmallVectorImpl< MachineInstr * > &MemInsns, AliasAnalysis *AA)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
static bool isConstant(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static const Function * getParent(const Value *V)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
DXIL Forward Handle Accesses
static bool isSigned(unsigned int Opcode)
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))
const int Hexagon_MEMH_OFFSET_MAX
Definition HexagonInstrInfo.cpp:110
const int Hexagon_MEMB_OFFSET_MAX
Definition HexagonInstrInfo.cpp:112
const int Hexagon_MEMH_OFFSET_MIN
Definition HexagonInstrInfo.cpp:111
const int Hexagon_MEMD_OFFSET_MAX
Definition HexagonInstrInfo.cpp:108
static cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
const int Hexagon_MEMD_OFFSET_MIN
Definition HexagonInstrInfo.cpp:109
const int Hexagon_ADDI_OFFSET_MAX
Definition HexagonInstrInfo.cpp:114
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
Definition HexagonInstrInfo.cpp:841
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
Definition HexagonInstrInfo.cpp:106
const int Hexagon_MEMW_OFFSET_MIN
Definition HexagonInstrInfo.cpp:107
cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
const int Hexagon_ADDI_OFFSET_MIN
Definition HexagonInstrInfo.cpp:115
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))
static void parseOperands(const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
Gather register def/uses from MI.
Definition HexagonInstrInfo.cpp:237
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
const int Hexagon_MEMB_OFFSET_MIN
Definition HexagonInstrInfo.cpp:113
static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
Calculate number of instructions excluding the debug instructions.
Definition HexagonInstrInfo.cpp:142
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI)
Definition HexagonInstrInfo.cpp:136
static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
Definition HexagonInstrInfo.cpp:852
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))
static bool isIntRegForSubInst(Register Reg)
Definition HexagonInstrInfo.cpp:131
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
Definition HexagonInstrInfo.cpp:259
#define HEXAGON_INSTR_SIZE
std::pair< Instruction::BinaryOps, Value * > OffsetOp
Find all possible pairs (BinOp, RHS) that BinOp V, RHS can be simplified.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first DebugLoc that has line number information, given a range of instructions.
static bool isUndef(const MachineInstr &MI)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t IntrinsicInst * II
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static StringRef getName(Value *V)
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
short getEquivalentHWInstr(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4323
int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const
Definition HexagonInstrInfo.cpp:3560
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
Definition HexagonInstrInfo.cpp:605
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition HexagonInstrInfo.cpp:1685
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
Definition HexagonInstrInfo.cpp:2346
short changeAddrMode_abs_io(short Opc) const
Definition HexagonInstrInfo.cpp:4771
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4465
short getRegForm(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4593
bool isVecALU(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2982
bool isCompoundBranchInstr(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2158
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
Definition HexagonInstrInfo.cpp:2278
bool isJumpR(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2380
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition HexagonInstrInfo.cpp:1887
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition HexagonInstrInfo.cpp:2085
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition HexagonInstrInfo.cpp:3211
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
Definition HexagonInstrInfo.cpp:4675
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Store the specified register of the given register class to the specified stack frame index.
Definition HexagonInstrInfo.cpp:963
bool isPredictedTaken(unsigned Opcode) const
Definition HexagonInstrInfo.cpp:2566
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2573
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Definition HexagonInstrInfo.cpp:289
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
Definition HexagonInstrInfo.cpp:4652
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
Definition HexagonInstrInfo.cpp:3877
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition HexagonInstrInfo.cpp:1748
unsigned getInvertedPredicatedOpcode(const int Opc) const
Definition HexagonInstrInfo.cpp:4400
bool isPureSlot0(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4453
bool doesNotReturn(const MachineInstr &CallMI) const
Definition HexagonInstrInfo.cpp:3130
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3943
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition HexagonInstrInfo.cpp:435
bool getPredReg(ArrayRef< MachineOperand > Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
Definition HexagonInstrInfo.cpp:4569
bool isPredicatedNew(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2530
bool isSignExtendingLoad(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2580
bool isVecAcc(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2978
bool reversePredSense(MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4718
bool isQFPMul(const MachineInstr *MF) const
Definition HexagonInstrInfo.cpp:4757
unsigned getAddrMode(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3301
MCInst getNop() const override
Definition HexagonInstrInfo.cpp:4803
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
Definition HexagonInstrInfo.cpp:2398
bool mayBeNewStore(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3203
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
Definition HexagonInstrInfo.cpp:2523
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
Definition HexagonInstrInfo.cpp:3105
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
Definition HexagonInstrInfo.cpp:4347
bool isAddrModeWithOffset(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4425
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
Definition HexagonInstrInfo.cpp:3092
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
Definition HexagonInstrInfo.cpp:2766
bool isBaseImmOffset(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2145
bool isAbsoluteSet(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2136
short changeAddrMode_io_pi(short Opc) const
Definition HexagonInstrInfo.cpp:4779
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Emit instructions to copy a pair of physical registers.
Definition HexagonInstrInfo.cpp:860
short changeAddrMode_pi_io(short Opc) const
Definition HexagonInstrInfo.cpp:4787
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition HexagonInstrInfo.cpp:1898
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition HexagonInstrInfo.cpp:1652
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition HexagonInstrInfo.cpp:809
bool isLoopN(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2446
bool isSpillPredRegOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2663
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition HexagonInstrInfo.cpp:405
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition HexagonInstrInfo.cpp:2091
bool isIndirectCall(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2355
short changeAddrMode_ur_rr(short Opc) const
Definition HexagonInstrInfo.cpp:4799
bool isValidAutoIncImm(const EVT VT, const int Offset) const
Definition HexagonInstrInfo.cpp:2729
bool hasNonExtEquivalent(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3144
bool isConstExtended(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2164
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
Definition HexagonInstrInfo.cpp:2062
int getCondOpcode(int Opc, bool sense) const
Definition HexagonInstrInfo.cpp:3617
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition HexagonInstrInfo.cpp:198
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4327
bool isAccumulator(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2140
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition HexagonInstrInfo.cpp:628
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
Definition HexagonInstrInfo.cpp:1988
bool PredOpcodeHasJMP_c(unsigned Opcode) const
Definition HexagonInstrInfo.cpp:3284
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Load the specified register of the given register class from the specified stack frame index.
Definition HexagonInstrInfo.cpp:1011
bool isNewValue(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2490
Register createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
Definition HexagonInstrInfo.cpp:2119
bool isDotCurInst(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2259
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
Definition HexagonInstrInfo.cpp:4736
bool isExtended(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2326
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition HexagonInstrInfo.cpp:823
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition HexagonInstrInfo.cpp:155
int getMaxValue(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4411
bool isPredicateLate(unsigned Opcode) const
Definition HexagonInstrInfo.cpp:2561
short changeAddrMode_rr_ur(short Opc) const
Definition HexagonInstrInfo.cpp:4795
bool hasPseudoInstrPair(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3179
bool isNewValueInst(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2500
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
Definition HexagonInstrInfo.cpp:1859
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition HexagonInstrInfo.cpp:2004
int getNonDotCurOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3649
bool isIndirectL4Return(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2366
unsigned reversePrediction(unsigned Opcode) const
Definition HexagonInstrInfo.cpp:4725
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition HexagonInstrInfo.cpp:2110
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4640
unsigned getMemAccessSize(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4508
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
Definition HexagonInstrInfo.cpp:3295
bool isComplex(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2149
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
Definition HexagonInstrInfo.cpp:1673
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
Definition HexagonInstrInfo.cpp:4742
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:1551
int getDotNewOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3750
void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const
Definition HexagonInstrInfo.cpp:4471
bool isMemOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2458
int getDotOldOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3892
short getPseudoInstrPair(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4589
bool hasUncondBranch(const MachineBasicBlock *B) const
Definition HexagonInstrInfo.cpp:3184
short getNonExtOpcode(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4545
bool isTailCall(const MachineInstr &MI) const override
Definition HexagonInstrInfo.cpp:2673
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
Definition HexagonInstrInfo.cpp:1667
bool isDeallocRet(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2213
HexagonInstrInfo(const HexagonSubtarget &ST)
Definition HexagonInstrInfo.cpp:120
unsigned getCExtOpNum(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3438
bool isSolo(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2658
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
Definition HexagonInstrInfo.cpp:1994
bool isLateSourceInstr(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2440
bool isDotNewInst(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2270
void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const
Definition HexagonInstrInfo.cpp:4489
bool isTC1(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2684
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition HexagonInstrInfo.cpp:1811
bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const
Definition HexagonInstrInfo.cpp:3249
unsigned getSize(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4601
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition HexagonInstrInfo.cpp:836
short changeAddrMode_io_abs(short Opc) const
Definition HexagonInstrInfo.cpp:4775
int getDotCurOp(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3629
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
Definition HexagonInstrInfo.cpp:1057
bool isExpr(unsigned OpType) const
Definition HexagonInstrInfo.cpp:2290
void genAllInsnTimingClasses(MachineFunction &MF) const
Definition HexagonInstrInfo.cpp:4696
bool isTC2Early(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2694
bool hasEHLabel(const MachineBasicBlock *B) const
Definition HexagonInstrInfo.cpp:3135
bool shouldSink(const MachineInstr &MI) const override
Definition HexagonInstrInfo.cpp:186
bool isZeroExtendingLoad(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3004
short changeAddrMode_rr_io(short Opc) const
Definition HexagonInstrInfo.cpp:4791
bool isHVXVec(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2723
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition HexagonInstrInfo.cpp:2228
short changeAddrMode_io_rr(short Opc) const
Definition HexagonInstrInfo.cpp:4783
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Definition HexagonInstrInfo.cpp:1742
bool mayBeCurLoad(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3196
bool getBundleNoShuf(const MachineInstr &MIB) const
Definition HexagonInstrInfo.cpp:4751
bool isNewValueJump(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2504
bool isTC4x(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2699
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
Definition HexagonInstrInfo.cpp:1690
bool isFloat(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2339
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition HexagonInstrInfo.cpp:2705
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, LocationSize &AccessSize) const
Definition HexagonInstrInfo.cpp:3311
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Definition HexagonInstrInfo.cpp:4391
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Definition HexagonInstrInfo.cpp:4648
uint64_t getType(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4635
bool isEndLoopN(unsigned Opcode) const
Definition HexagonInstrInfo.cpp:2285
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
Definition HexagonInstrInfo.cpp:3343
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
Definition HexagonInstrInfo.cpp:1775
bool isExtendable(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2304
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition HexagonInstrInfo.cpp:4662
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:3445
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition HexagonInstrInfo.cpp:387
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
Definition HexagonInstrInfo.cpp:3380
bool isPredicatedTrue(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2542
bool isNewValueStore(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2512
int getMinValue(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:4531
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition HexagonInstrInfo.cpp:2990
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
Definition HexagonInstrInfo.cpp:3533
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition HexagonInstrInfo.cpp:3083
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition HexagonInstrInfo.cpp:337
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
Definition HexagonInstrInfo.cpp:3791
bool isTC2(const MachineInstr &MI) const
Definition HexagonInstrInfo.cpp:2689
Register getStackRegister() const
Register getFrameRegister(const MachineFunction &MF) const override
Itinerary data supplied by a subtarget to be used by a target.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
A set of physical registers with utility functions to track liveness when walking backward/forward th...
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * > > &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
bool available(const MachineRegisterInfo &MRI, MCRegister Reg) const
Returns true if register Reg and no aliasing register is in the set.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
bool contains(MCRegister Reg) const
Returns true if register Reg is contained in the set.
static LocationSize precise(uint64_t Value)
Represents a single loop in the control flow graph.
This class is intended to be used as a base class for asm properties and features specific to the tar...
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
StringRef getCommentString() const
const char * getSeparatorString() const
MCInstBuilder & addInst(const MCInst *Val)
Add a new MCInst operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
instr_iterator instr_begin()
MachineInstrBundleIterator< const MachineInstr > const_iterator
LLVM_ABI iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Instructions::iterator instr_iterator
instr_iterator instr_end()
Instructions::const_iterator const_instr_iterator
iterator_range< pred_iterator > predecessors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
BasicBlockListType::iterator iterator
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
instr_iterator getInstrIterator() const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
unsigned getNumOperands() const
Retuns the total number of operands.
LLVM_ABI unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
LLVM_ABI bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
LLVM_ABI bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
LLVM_ABI void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
A description of a memory reference used in the backend.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
void addTargetFlag(unsigned F)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
size_t count(char C) const
Return the number of occurrences of C in the string.
Object returned by analyzeLoopForPipelining.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Primary interface to the complete machine description for the target machine.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSlot0Only(unsigned units)
HexagonII - This namespace holds all of the target specific flags that instruction info tracks.
unsigned const TypeCVI_LAST
@ RestrictNoSlot1StoreMask
@ RestrictNoSlot1StorePos
unsigned const TypeCVI_FIRST
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
bool is_TC1(unsigned SchedClass)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
auto reverse(ContainerTy &&C)
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
FunctionAddr VTableAddr Count
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool is_TC2(unsigned SchedClass)
unsigned getUndefRegState(bool B)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
bool is_TC2early(unsigned SchedClass)
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr bool isShiftedInt(int64_t x)
Checks if a signed integer is an N bit number shifted left by S.
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
bool isSpace(char C)
Checks whether character C is whitespace in the "C" locale.
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
constexpr bool isShiftedUInt(uint64_t x)
Checks if a unsigned integer is an N bit number shifted left by S.
LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool is_TC4x(unsigned SchedClass)
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
These values represent a non-pipelined step in the execution of an instruction.
uint64_t FuncUnits
Bitmask representing a set of functional units.
FuncUnits getUnits() const
Returns the choice of FUs.
This class contains a discriminated union of information about pointers in memory operands,...
static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.