LLVM: lib/Target/Hexagon/HexagonInstrInfo.cpp Source File (original) (raw)
1
2
3
4
5
6
7
8
9
10
11
12
54#include
55#include
56#include
57#include
58#include
59#include
60#include
61#include
62
63using namespace llvm;
64
65#define DEBUG_TYPE "hexagon-instrinfo"
66
67#define GET_INSTRINFO_CTOR_DTOR
68#define GET_INSTRMAP_INFO
70#include "HexagonGenDFAPacketizer.inc"
71#include "HexagonGenInstrInfo.inc"
72
74 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75 "packetization boundary."));
76
79
81 "disable-hexagon-nv-schedule", cl::Hidden,
82 cl::desc("Disable schedule adjustment for new value stores."));
83
86 cl::desc("Enable timing class latency"));
87
90 cl::desc("Enable vec alu forwarding"));
91
94 cl::desc("Enable vec acc forwarding"));
95
98 cl::desc("branch relax asm"));
99
102 cl::desc("Use the DFA based hazard recognizer."));
103
104
115
116
117void HexagonInstrInfo::anchor() {}
118
120 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
121 Subtarget(ST) {}
122
123namespace llvm {
124namespace HexagonFUnits {
126}
127}
128
130 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
131 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
132}
133
137}
138
139
142 unsigned Count = 0;
143 for (; MIB != MIE; ++MIB) {
144 if (!MIB->isDebugInstr())
145 ++Count;
146 }
147 return Count;
148}
149
150
151
152
154
155 if (!(MI.getMF()->getFunction().hasOptSize()))
156 return MI.isAsCheapAsAMove();
157
158 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
159 auto Op = MI.getOperand(1);
160
161
162 if (Op.isGlobal())
163 return false;
164
165
166 if (Op.isImm()) {
167 int64_t Imm = Op.getImm();
168 if (!isInt<16>(Imm))
169 return false;
170 }
171 }
172 return MI.isAsCheapAsAMove();
173}
174
175
176
177
178
179
180
181
182
183
185
186
187 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
188 return false;
189 return true;
190}
191
192
193
194
195
199 unsigned LOOPi;
200 unsigned LOOPr;
201 if (EndLoopOp == Hexagon::ENDLOOP0) {
202 LOOPi = Hexagon::J2_loop0i;
203 LOOPr = Hexagon::J2_loop0r;
204 } else {
205 LOOPi = Hexagon::J2_loop1i;
206 LOOPr = Hexagon::J2_loop1r;
207 }
208
209
211
212 if (!Visited.insert(PB).second)
213 continue;
214 if (PB == BB)
215 continue;
217 unsigned Opc = I.getOpcode();
218 if (Opc == LOOPi || Opc == LOOPr)
219 return &I;
220
221
222 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
223 return nullptr;
224 }
225
228 }
229 return nullptr;
230}
231
232
233
234
238 Uses.clear();
239
241 if (!MO.isReg())
242 continue;
243
245 if (!Reg)
246 continue;
247
248 if (MO.isUse())
249 Uses.push_back(MO.getReg());
250
251 if (MO.isDef())
253 }
254}
255
256
258 switch (Ga) {
260 default:
261 return false;
278 }
279 return false;
280}
281
282
283
284
285
286
288 int &FrameIndex) const {
289 switch (MI.getOpcode()) {
290 default:
291 break;
292 case Hexagon::L2_loadri_io:
293 case Hexagon::L2_loadrd_io:
294 case Hexagon::V6_vL32b_ai:
295 case Hexagon::V6_vL32b_nt_ai:
296 case Hexagon::V6_vL32Ub_ai:
297 case Hexagon::LDriw_pred:
298 case Hexagon::LDriw_ctr:
299 case Hexagon::PS_vloadrq_ai:
300 case Hexagon::PS_vloadrw_ai:
301 case Hexagon::PS_vloadrw_nt_ai: {
303 if (!OpFI.isFI())
304 return 0;
306 if (!OpOff.isImm() || OpOff.getImm() != 0)
307 return 0;
308 FrameIndex = OpFI.getIndex();
309 return MI.getOperand(0).getReg();
310 }
311
312 case Hexagon::L2_ploadrit_io:
313 case Hexagon::L2_ploadrif_io:
314 case Hexagon::L2_ploadrdt_io:
315 case Hexagon::L2_ploadrdf_io: {
317 if (!OpFI.isFI())
318 return 0;
320 if (!OpOff.isImm() || OpOff.getImm() != 0)
321 return 0;
322 FrameIndex = OpFI.getIndex();
323 return MI.getOperand(0).getReg();
324 }
325 }
326
327 return 0;
328}
329
330
331
332
333
334
336 int &FrameIndex) const {
337 switch (MI.getOpcode()) {
338 default:
339 break;
340 case Hexagon::S2_storerb_io:
341 case Hexagon::S2_storerh_io:
342 case Hexagon::S2_storeri_io:
343 case Hexagon::S2_storerd_io:
344 case Hexagon::V6_vS32b_ai:
345 case Hexagon::V6_vS32Ub_ai:
346 case Hexagon::STriw_pred:
347 case Hexagon::STriw_ctr:
348 case Hexagon::PS_vstorerq_ai:
349 case Hexagon::PS_vstorerw_ai: {
351 if (!OpFI.isFI())
352 return 0;
354 if (!OpOff.isImm() || OpOff.getImm() != 0)
355 return 0;
356 FrameIndex = OpFI.getIndex();
357 return MI.getOperand(2).getReg();
358 }
359
360 case Hexagon::S2_pstorerbt_io:
361 case Hexagon::S2_pstorerbf_io:
362 case Hexagon::S2_pstorerht_io:
363 case Hexagon::S2_pstorerhf_io:
364 case Hexagon::S2_pstorerit_io:
365 case Hexagon::S2_pstorerif_io:
366 case Hexagon::S2_pstorerdt_io:
367 case Hexagon::S2_pstorerdf_io: {
369 if (!OpFI.isFI())
370 return 0;
372 if (!OpOff.isImm() || OpOff.getImm() != 0)
373 return 0;
374 FrameIndex = OpFI.getIndex();
375 return MI.getOperand(3).getReg();
376 }
377 }
378
379 return 0;
380}
381
382
383
384
388 if (MI.isBundle()) {
391 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
393 return true;
394 return false;
395 }
396
398}
399
400
401
402
406 if (MI.isBundle()) {
409 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
411 return true;
412 return false;
413 }
414
416}
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
437 bool AllowModify) const {
438 TBB = nullptr;
439 FBB = nullptr;
440 Cond.clear();
441
442
445 return false;
446
447
448
449
450
451
452
453
454
455
456
457
458
459 do {
460 --I;
461 if (I->isEHLabel())
462
463 return true;
465
467 --I;
468
469 while (I->isDebugInstr()) {
471 return false;
472 --I;
473 }
474
475 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
476 I->getOperand(0).isMBB();
477
478 if (AllowModify && JumpToBlock &&
480 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
481 I->eraseFromParent();
484 return false;
485 --I;
486 }
487 if (!isUnpredicatedTerminator(*I))
488 return false;
489
490
493
494 while (true) {
495 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
496 if (!SecondLastInst)
497 SecondLastInst = &*I;
498 else
499
500 return true;
501 }
503 break;
504 --I;
505 }
506
507 int LastOpcode = LastInst->getOpcode();
508 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
509
510
511 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
512 return true;
513 if (SecLastOpcode == Hexagon::J2_jump &&
515 return true;
516
518 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
519
520 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
521 return true;
522
523
524 if (LastInst && !SecondLastInst) {
525 if (LastOpcode == Hexagon::J2_jump) {
527 return false;
528 }
533 return false;
534 }
535 if (LastOpcodeHasJMP_c) {
539 return false;
540 }
541
547 return false;
548 }
550 << " with one jump\n";);
551
552 return true;
553 }
554
556 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
557 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
559 return true;
564 return false;
565 }
566
567
568 if (SecLastOpcodeHasNVJump &&
570 (LastOpcode == Hexagon::J2_jump)) {
576 return false;
577 }
578
579
580
581 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
584 if (AllowModify)
585 I->eraseFromParent();
586 return false;
587 }
588
589
590 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
595 return false;
596 }
598 << " with two jumps";);
599
600 return true;
601}
602
604 int *BytesRemoved) const {
605 assert(!BytesRemoved && "code size not handled");
606
609 unsigned Count = 0;
611 --I;
612 if (I->isDebugInstr())
613 continue;
614
615 if (->isBranch())
616 return Count;
617 if (Count && (I->getOpcode() == Hexagon::J2_jump))
618 llvm_unreachable("Malformed basic block: unconditional branch not last");
621 ++Count;
622 }
623 return Count;
624}
625
631 int *BytesAdded) const {
632 unsigned BOpc = Hexagon::J2_jump;
633 unsigned BccOpc = Hexagon::J2_jumpt;
635 assert(TBB && "insertBranch must not be told to insert a fallthrough");
636 assert(!BytesAdded && "code size not handled");
637
638
639
640
641 if (.empty() && Cond[0].isImm())
642 BccOpc = Cond[0].getImm();
643
644 if (!FBB) {
645 if (Cond.empty()) {
646
647
648
649
659 }
662 int EndLoopOp = Cond[0].getImm();
664
665
668 VisitedBBs);
669 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
670 Loop->getOperand(0).setMBB(TBB);
671
674 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
675
676
677
688 } else
690 } else {
691 assert((Cond.size() == 2) && "Malformed cond vector");
695 }
696 return 1;
697 }
699 "Cond. cannot be empty when multiple branchings are required");
701 "NV-jump cannot be inserted with another branch");
702
704 int EndLoopOp = Cond[0].getImm();
706
707
710 VisitedBBs);
711 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
712 Loop->getOperand(0).setMBB(TBB);
713
715 } else {
719 }
721
722 return 2;
723}
724
725namespace {
730 int64_t TripCount;
733
734public:
739
740
741 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
742 ? -1
743 : Loop->getOperand(1).getImm();
744 if (TripCount == -1)
745 LoopCount = Loop->getOperand(1).getReg();
746 }
747
748 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
749
750 return MI == EndLoop;
751 }
752
753 std::optional createTripCountGreaterCondition(
756 if (TripCount == -1) {
757
760 TII->get(Hexagon::C2_cmpgtui), Done)
765 return {};
766 }
767
768 return TripCount > TC;
769 }
770
774 }
775
776 void adjustTripCount(int TripCountAdjust) override {
777
778
779 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
780 Loop->getOpcode() == Hexagon::J2_loop1i) {
781 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
782 assert(TripCount > 0 && "Can't create an empty or negative loop!");
783 Loop->getOperand(1).setImm(TripCount);
784 return;
785 }
786
787
788
789 Register LoopCount = Loop->getOperand(1).getReg();
792 TII->get(Hexagon::A2_addi), NewLoopCount)
794 .addImm(TripCountAdjust);
795 Loop->getOperand(1).setReg(NewLoopCount);
796 }
797
798 void disposed() override { Loop->eraseFromParent(); }
799};
800}
801
802std::unique_ptrTargetInstrInfo::PipelinerLoopInfo
804
806
810 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
811 if (LoopInst)
812 return std::make_unique(LoopInst, &*I);
813 }
814 return nullptr;
815}
816
818 unsigned NumCycles, unsigned ExtraPredCycles,
821}
822
824 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
825 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
826 const {
828}
829
832 return NumInstrs <= 4;
833}
834
840 for (auto I = B.begin(); I != E; ++I) {
841 Clobbers.clear();
843 }
844}
845
850 for (auto I = B.rbegin(); I != E; ++I)
852}
853
858 bool RenamableDest,
859 bool RenamableSrc) const {
862
863 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
865 .addReg(SrcReg, KillFlag);
866 return;
867 }
868 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
870 .addReg(SrcReg, KillFlag);
871 return;
872 }
873 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
874
877 return;
878 }
879 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
880 Hexagon::IntRegsRegClass.contains(SrcReg)) {
882 .addReg(SrcReg, KillFlag);
883 return;
884 }
885 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
886 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
888 .addReg(SrcReg, KillFlag);
889 return;
890 }
891 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
892 Hexagon::IntRegsRegClass.contains(SrcReg)) {
894 .addReg(SrcReg, KillFlag);
895 return;
896 }
897 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
898 Hexagon::IntRegsRegClass.contains(DestReg)) {
900 .addReg(SrcReg, KillFlag);
901 return;
902 }
903 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
904 Hexagon::PredRegsRegClass.contains(DestReg)) {
906 .addReg(SrcReg, KillFlag);
907 return;
908 }
909 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
910 Hexagon::IntRegsRegClass.contains(DestReg)) {
912 .addReg(SrcReg, KillFlag);
913 return;
914 }
915 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
917 addReg(SrcReg, KillFlag);
918 return;
919 }
920 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
923 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
924 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
928 .addReg(SrcHi, KillFlag | UndefHi)
929 .addReg(SrcLo, KillFlag | UndefLo);
930 return;
931 }
932 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
935 .addReg(SrcReg, KillFlag);
936 return;
937 }
938 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
939 Hexagon::HvxVRRegClass.contains(DestReg)) {
941 return;
942 }
943 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
944 Hexagon::HvxVRRegClass.contains(SrcReg)) {
946 return;
947 }
948
949#ifndef NDEBUG
950
952 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
953#endif
955}
956
959 Register SrcReg, bool isKill, int FI,
967
971
972 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
976 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
980 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
984 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
988 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
992 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
996 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1000 } else {
1002 }
1003}
1004
1014
1018
1019 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1022 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1025 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1028 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1031 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1034 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1037 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1040 } else {
1041 llvm_unreachable("Can't store this register to stack slot");
1042 }
1043}
1044
1045
1046
1047
1048
1049
1050
1058 unsigned Opc = MI.getOpcode();
1059
1060 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1061 Register Mx = MI.getOperand(MxOp).getReg();
1062 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1064 .add(MI.getOperand((HasImm ? 5 : 4)));
1066 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1067 if (HasImm)
1068 MIB.add(MI.getOperand(4));
1071 return true;
1072 };
1073
1075 if (MI.memoperands().empty())
1076 return false;
1078 return MMO->getAlign() >= NeedAlign;
1079 });
1080 };
1081
1082 switch (Opc) {
1083 case Hexagon::PS_call_instrprof_custom: {
1084 auto Op0 = MI.getOperand(0);
1085 assert(Op0.isGlobal() &&
1086 "First operand must be a global containing handler name.");
1087 const GlobalValue *NameVar = Op0.getGlobal();
1088 const GlobalVariable *GV = dyn_cast(NameVar);
1089 auto *Arr = cast(GV->getInitializer());
1090 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1091
1093
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1116 MIB.addExternalSymbol(cstr);
1118 return true;
1119 }
1120 case TargetOpcode::COPY: {
1127 }
1129 return true;
1130 }
1131 case Hexagon::PS_aligna:
1134 .addImm(-MI.getOperand(1).getImm());
1136 return true;
1137 case Hexagon::V6_vassignp: {
1138 Register SrcReg = MI.getOperand(1).getReg();
1139 Register DstReg = MI.getOperand(0).getReg();
1140 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1141 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1143 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1144 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1147 .addReg(SrcHi, UndefHi)
1148 .addReg(SrcLo, Kill | UndefLo);
1150 return true;
1151 }
1152 case Hexagon::V6_lo: {
1153 Register SrcReg = MI.getOperand(1).getReg();
1154 Register DstReg = MI.getOperand(0).getReg();
1155 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1158 MRI.clearKillFlags(SrcSubLo);
1159 return true;
1160 }
1161 case Hexagon::V6_hi: {
1162 Register SrcReg = MI.getOperand(1).getReg();
1163 Register DstReg = MI.getOperand(0).getReg();
1164 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1167 MRI.clearKillFlags(SrcSubHi);
1168 return true;
1169 }
1170 case Hexagon::PS_vloadrv_ai: {
1171 Register DstReg = MI.getOperand(0).getReg();
1174 int Offset = MI.getOperand(2).getImm();
1175 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1176 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1177 : Hexagon::V6_vL32Ub_ai;
1183 return true;
1184 }
1185 case Hexagon::PS_vloadrw_ai: {
1186 Register DstReg = MI.getOperand(0).getReg();
1189 int Offset = MI.getOperand(2).getImm();
1190 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1191 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1192 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1193 : Hexagon::V6_vL32Ub_ai;
1195 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1200 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1205 return true;
1206 }
1207 case Hexagon::PS_vstorerv_ai: {
1212 int Offset = MI.getOperand(1).getImm();
1213 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1214 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1215 : Hexagon::V6_vS32Ub_ai;
1222 return true;
1223 }
1224 case Hexagon::PS_vstorerw_ai: {
1225 Register SrcReg = MI.getOperand(2).getReg();
1228 int Offset = MI.getOperand(1).getImm();
1229 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1230 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1231 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1232 : Hexagon::V6_vS32Ub_ai;
1236 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1241 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1244 return true;
1245 }
1246 case Hexagon::PS_true: {
1247 Register Reg = MI.getOperand(0).getReg();
1252 return true;
1253 }
1254 case Hexagon::PS_false: {
1255 Register Reg = MI.getOperand(0).getReg();
1260 return true;
1261 }
1262 case Hexagon::PS_qtrue: {
1267 return true;
1268 }
1269 case Hexagon::PS_qfalse: {
1274 return true;
1275 }
1276 case Hexagon::PS_vdd0: {
1277 Register Vd = MI.getOperand(0).getReg();
1282 return true;
1283 }
1284 case Hexagon::PS_vmulw: {
1285
1286 Register DstReg = MI.getOperand(0).getReg();
1287 Register Src1Reg = MI.getOperand(1).getReg();
1288 Register Src2Reg = MI.getOperand(2).getReg();
1289 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1290 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1291 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1292 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1294 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1298 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1302 MRI.clearKillFlags(Src1SubHi);
1303 MRI.clearKillFlags(Src1SubLo);
1304 MRI.clearKillFlags(Src2SubHi);
1305 MRI.clearKillFlags(Src2SubLo);
1306 return true;
1307 }
1308 case Hexagon::PS_vmulw_acc: {
1309
1310 Register DstReg = MI.getOperand(0).getReg();
1311 Register Src1Reg = MI.getOperand(1).getReg();
1312 Register Src2Reg = MI.getOperand(2).getReg();
1313 Register Src3Reg = MI.getOperand(3).getReg();
1314 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1315 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1316 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1317 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1318 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1319 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1321 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1326 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1331 MRI.clearKillFlags(Src1SubHi);
1332 MRI.clearKillFlags(Src1SubLo);
1333 MRI.clearKillFlags(Src2SubHi);
1334 MRI.clearKillFlags(Src2SubLo);
1335 MRI.clearKillFlags(Src3SubHi);
1336 MRI.clearKillFlags(Src3SubLo);
1337 return true;
1338 }
1339 case Hexagon::PS_pselect: {
1352 if (Rd != Rs)
1354 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1356 if (Rd != Rt)
1361 return true;
1362 }
1363 case Hexagon::PS_vselect: {
1373
1375 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1376 : PState;
1378 .add(Op0)
1380 .add(Op2);
1381 if (IsDestLive)
1383 IsDestLive = true;
1384 }
1387 .add(Op0)
1388 .addReg(PReg, PState)
1389 .add(Op3);
1390 if (IsDestLive)
1392 }
1394 return true;
1395 }
1396 case Hexagon::PS_wselect: {
1406
1408 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1409 : PState;
1410 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1411 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1413 .add(Op0)
1417 if (IsDestLive)
1419 IsDestLive = true;
1420 }
1422 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1423 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1425 .add(Op0)
1426 .addReg(PReg, PState)
1429 if (IsDestLive)
1431 }
1433 return true;
1434 }
1435
1436 case Hexagon::PS_crash: {
1437
1439 public:
1442
1444 return false;
1445 }
1447 return false;
1448 }
1450 return false;
1451 }
1452 void printCustom(raw_ostream &OS) const override {
1453 OS << "MisalignedCrash";
1454 }
1455 };
1456
1457 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1463 .addImm(0xBADC0FEE)
1466 return true;
1467 }
1468
1469 case Hexagon::PS_tailcall_i:
1470 MI.setDesc(get(Hexagon::J2_jump));
1471 return true;
1472 case Hexagon::PS_tailcall_r:
1473 case Hexagon::PS_jmpret:
1474 MI.setDesc(get(Hexagon::J2_jumpr));
1475 return true;
1476 case Hexagon::PS_jmprett:
1477 MI.setDesc(get(Hexagon::J2_jumprt));
1478 return true;
1479 case Hexagon::PS_jmpretf:
1480 MI.setDesc(get(Hexagon::J2_jumprf));
1481 return true;
1482 case Hexagon::PS_jmprettnewpt:
1483 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1484 return true;
1485 case Hexagon::PS_jmpretfnewpt:
1486 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1487 return true;
1488 case Hexagon::PS_jmprettnew:
1489 MI.setDesc(get(Hexagon::J2_jumprtnew));
1490 return true;
1491 case Hexagon::PS_jmpretfnew:
1492 MI.setDesc(get(Hexagon::J2_jumprfnew));
1493 return true;
1494
1495 case Hexagon::PS_loadrub_pci:
1496 return RealCirc(Hexagon::L2_loadrub_pci, true, 4);
1497 case Hexagon::PS_loadrb_pci:
1498 return RealCirc(Hexagon::L2_loadrb_pci, true, 4);
1499 case Hexagon::PS_loadruh_pci:
1500 return RealCirc(Hexagon::L2_loadruh_pci, true, 4);
1501 case Hexagon::PS_loadrh_pci:
1502 return RealCirc(Hexagon::L2_loadrh_pci, true, 4);
1503 case Hexagon::PS_loadri_pci:
1504 return RealCirc(Hexagon::L2_loadri_pci, true, 4);
1505 case Hexagon::PS_loadrd_pci:
1506 return RealCirc(Hexagon::L2_loadrd_pci, true, 4);
1507 case Hexagon::PS_loadrub_pcr:
1508 return RealCirc(Hexagon::L2_loadrub_pcr, false, 3);
1509 case Hexagon::PS_loadrb_pcr:
1510 return RealCirc(Hexagon::L2_loadrb_pcr, false, 3);
1511 case Hexagon::PS_loadruh_pcr:
1512 return RealCirc(Hexagon::L2_loadruh_pcr, false, 3);
1513 case Hexagon::PS_loadrh_pcr:
1514 return RealCirc(Hexagon::L2_loadrh_pcr, false, 3);
1515 case Hexagon::PS_loadri_pcr:
1516 return RealCirc(Hexagon::L2_loadri_pcr, false, 3);
1517 case Hexagon::PS_loadrd_pcr:
1518 return RealCirc(Hexagon::L2_loadrd_pcr, false, 3);
1519 case Hexagon::PS_storerb_pci:
1520 return RealCirc(Hexagon::S2_storerb_pci, true, 3);
1521 case Hexagon::PS_storerh_pci:
1522 return RealCirc(Hexagon::S2_storerh_pci, true, 3);
1523 case Hexagon::PS_storerf_pci:
1524 return RealCirc(Hexagon::S2_storerf_pci, true, 3);
1525 case Hexagon::PS_storeri_pci:
1526 return RealCirc(Hexagon::S2_storeri_pci, true, 3);
1527 case Hexagon::PS_storerd_pci:
1528 return RealCirc(Hexagon::S2_storerd_pci, true, 3);
1529 case Hexagon::PS_storerb_pcr:
1530 return RealCirc(Hexagon::S2_storerb_pcr, false, 2);
1531 case Hexagon::PS_storerh_pcr:
1532 return RealCirc(Hexagon::S2_storerh_pcr, false, 2);
1533 case Hexagon::PS_storerf_pcr:
1534 return RealCirc(Hexagon::S2_storerf_pcr, false, 2);
1535 case Hexagon::PS_storeri_pcr:
1536 return RealCirc(Hexagon::S2_storeri_pcr, false, 2);
1537 case Hexagon::PS_storerd_pcr:
1538 return RealCirc(Hexagon::S2_storerd_pcr, false, 2);
1539 }
1540
1541 return false;
1542}
1543
1548 unsigned Opc = MI.getOpcode();
1550
1551 switch (Opc) {
1552 case Hexagon::V6_vgathermh_pseudo:
1559 .addImm(MI.getOperand(1).getImm())
1560 .addReg(Hexagon::VTMP);
1562 return First.getInstrIterator();
1563
1564 case Hexagon::V6_vgathermw_pseudo:
1571 .addImm(MI.getOperand(1).getImm())
1572 .addReg(Hexagon::VTMP);
1574 return First.getInstrIterator();
1575
1576 case Hexagon::V6_vgathermhw_pseudo:
1583 .addImm(MI.getOperand(1).getImm())
1584 .addReg(Hexagon::VTMP);
1586 return First.getInstrIterator();
1587
1588 case Hexagon::V6_vgathermhq_pseudo:
1596 .addImm(MI.getOperand(1).getImm())
1597 .addReg(Hexagon::VTMP);
1599 return First.getInstrIterator();
1600
1601 case Hexagon::V6_vgathermwq_pseudo:
1609 .addImm(MI.getOperand(1).getImm())
1610 .addReg(Hexagon::VTMP);
1612 return First.getInstrIterator();
1613
1614 case Hexagon::V6_vgathermhwq_pseudo:
1622 .addImm(MI.getOperand(1).getImm())
1623 .addReg(Hexagon::VTMP);
1625 return First.getInstrIterator();
1626 }
1627
1628 return MI.getIterator();
1629}
1630
1631
1632
1635 if (Cond.empty())
1636 return true;
1637 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1638 unsigned opcode = Cond[0].getImm();
1639
1640 assert(get(opcode).isBranch() && "Should be a branching condition.");
1642 return true;
1644 Cond[0].setImm(NewOpcode);
1645 return false;
1646}
1647
1652}
1653
1656}
1657
1658
1659
1660
1661
1662
1663
1664
1665
1667 const uint64_t F = MI.getDesc().TSFlags;
1669}
1670
1676 return false;
1677 }
1678 int Opc = MI.getOpcode();
1681
1682
1683
1684
1685
1686
1689 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1691 unsigned NOp = 0, NumOps = MI.getNumOperands();
1692 while (NOp < NumOps) {
1694 if (.isReg() ||
.isDef() || Op.isImplicit())
1695 break;
1697 NOp++;
1698 }
1699
1701 unsigned PredRegPos, PredRegFlags;
1702 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1703 (void)GotPredReg;
1705 T.addReg(PredReg, PredRegFlags);
1706 while (NOp < NumOps)
1707 T.add(MI.getOperand(NOp++));
1708
1709 MI.setDesc(get(PredOpc));
1710 while (unsigned n = MI.getNumOperands())
1711 MI.removeOperand(n-1);
1712 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1713 MI.addOperand(T->getOperand(i));
1714
1716 B.erase(TI);
1717
1719 MRI.clearKillFlags(PredReg);
1720 return true;
1721}
1722
1725
1726 return false;
1727}
1728
1730 std::vector &Pred,
1731 bool SkipDead) const {
1733
1735 if (MO.isReg()) {
1736 if (!MO.isDef())
1737 continue;
1738 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1739 if (RC == &Hexagon::PredRegsRegClass) {
1740 Pred.push_back(MO);
1741 return true;
1742 }
1743 continue;
1744 } else if (MO.isRegMask()) {
1745 for (Register PR : Hexagon::PredRegsRegClass) {
1746 if (.modifiesRegister(PR, &HRI))
1747 continue;
1748 Pred.push_back(MO);
1749 return true;
1750 }
1751 }
1752 }
1753 return false;
1754}
1755
1757 if (.getDesc().isPredicable())
1758 return false;
1759
1762 return false;
1763 }
1764
1765
1767 switch (MI.getOpcode()) {
1768 case Hexagon::V6_vL32b_ai:
1769 case Hexagon::V6_vL32b_pi:
1770 case Hexagon::V6_vL32b_ppu:
1771 case Hexagon::V6_vL32b_cur_ai:
1772 case Hexagon::V6_vL32b_cur_pi:
1773 case Hexagon::V6_vL32b_cur_ppu:
1774 case Hexagon::V6_vL32b_nt_ai:
1775 case Hexagon::V6_vL32b_nt_pi:
1776 case Hexagon::V6_vL32b_nt_ppu:
1777 case Hexagon::V6_vL32b_tmp_ai:
1778 case Hexagon::V6_vL32b_tmp_pi:
1779 case Hexagon::V6_vL32b_tmp_ppu:
1780 case Hexagon::V6_vL32b_nt_cur_ai:
1781 case Hexagon::V6_vL32b_nt_cur_pi:
1782 case Hexagon::V6_vL32b_nt_cur_ppu:
1783 case Hexagon::V6_vL32b_nt_tmp_ai:
1784 case Hexagon::V6_vL32b_nt_tmp_pi:
1785 case Hexagon::V6_vL32b_nt_tmp_ppu:
1786 return false;
1787 }
1788 }
1789 return true;
1790}
1791
1795
1796
1797
1798
1799
1800
1801 if (MI.isDebugInstr())
1802 return false;
1803
1804
1805 if (MI.isCall()) {
1806
1808 return true;
1809
1810
1812 if (I->isEHPad())
1813 return true;
1814 }
1815
1816
1817 if (MI.getDesc().isTerminator() || MI.isPosition())
1818 return true;
1819
1820
1821 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1822 return true;
1823
1825 return true;
1826
1827 return false;
1828}
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1844
1845 bool atInsnStart = true;
1846 unsigned Length = 0;
1848 for (; *Str; ++Str) {
1851 atInsnStart = true;
1852 if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1853 Length += MaxInstLength;
1854 atInsnStart = false;
1855 }
1858 atInsnStart = false;
1859 }
1860
1861
1865}
1866
1873}
1874
1875
1876
1877
1878
1880 Register &SrcReg2, int64_t &Mask,
1881 int64_t &Value) const {
1882 unsigned Opc = MI.getOpcode();
1883
1884
1885 switch (Opc) {
1886 case Hexagon::C2_cmpeq:
1887 case Hexagon::C2_cmpeqp:
1888 case Hexagon::C2_cmpgt:
1889 case Hexagon::C2_cmpgtp:
1890 case Hexagon::C2_cmpgtu:
1891 case Hexagon::C2_cmpgtup:
1892 case Hexagon::C4_cmpneq:
1893 case Hexagon::C4_cmplte:
1894 case Hexagon::C4_cmplteu:
1895 case Hexagon::C2_cmpeqi:
1896 case Hexagon::C2_cmpgti:
1897 case Hexagon::C2_cmpgtui:
1898 case Hexagon::C4_cmpneqi:
1899 case Hexagon::C4_cmplteui:
1900 case Hexagon::C4_cmpltei:
1901 SrcReg = MI.getOperand(1).getReg();
1902 Mask = ~0;
1903 break;
1904 case Hexagon::A4_cmpbeq:
1905 case Hexagon::A4_cmpbgt:
1906 case Hexagon::A4_cmpbgtu:
1907 case Hexagon::A4_cmpbeqi:
1908 case Hexagon::A4_cmpbgti:
1909 case Hexagon::A4_cmpbgtui:
1910 SrcReg = MI.getOperand(1).getReg();
1911 Mask = 0xFF;
1912 break;
1913 case Hexagon::A4_cmpheq:
1914 case Hexagon::A4_cmphgt:
1915 case Hexagon::A4_cmphgtu:
1916 case Hexagon::A4_cmpheqi:
1917 case Hexagon::A4_cmphgti:
1918 case Hexagon::A4_cmphgtui:
1919 SrcReg = MI.getOperand(1).getReg();
1920 Mask = 0xFFFF;
1921 break;
1922 }
1923
1924
1925 switch (Opc) {
1926 case Hexagon::C2_cmpeq:
1927 case Hexagon::C2_cmpeqp:
1928 case Hexagon::C2_cmpgt:
1929 case Hexagon::C2_cmpgtp:
1930 case Hexagon::C2_cmpgtu:
1931 case Hexagon::C2_cmpgtup:
1932 case Hexagon::A4_cmpbeq:
1933 case Hexagon::A4_cmpbgt:
1934 case Hexagon::A4_cmpbgtu:
1935 case Hexagon::A4_cmpheq:
1936 case Hexagon::A4_cmphgt:
1937 case Hexagon::A4_cmphgtu:
1938 case Hexagon::C4_cmpneq:
1939 case Hexagon::C4_cmplte:
1940 case Hexagon::C4_cmplteu:
1941 SrcReg2 = MI.getOperand(2).getReg();
1943 return true;
1944
1945 case Hexagon::C2_cmpeqi:
1946 case Hexagon::C2_cmpgtui:
1947 case Hexagon::C2_cmpgti:
1948 case Hexagon::C4_cmpneqi:
1949 case Hexagon::C4_cmplteui:
1950 case Hexagon::C4_cmpltei:
1951 case Hexagon::A4_cmpbeqi:
1952 case Hexagon::A4_cmpbgti:
1953 case Hexagon::A4_cmpbgtui:
1954 case Hexagon::A4_cmpheqi:
1955 case Hexagon::A4_cmphgti:
1956 case Hexagon::A4_cmphgtui: {
1957 SrcReg2 = 0;
1959 if (!Op2.isImm())
1960 return false;
1961 Value = MI.getOperand(2).getImm();
1962 return true;
1963 }
1964 }
1965
1966 return false;
1967}
1968
1971 unsigned *PredCost) const {
1973}
1974
1978 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1979}
1980
1981
1982
1983
1984
1989 return false;
1990
1991
1992
1994 return true;
1995
1996
1997 unsigned BasePosA, OffsetPosA;
1999 return false;
2002 unsigned BaseSubA = BaseA.getSubReg();
2003
2004
2005 unsigned BasePosB, OffsetPosB;
2007 return false;
2010 unsigned BaseSubB = BaseB.getSubReg();
2011
2012 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2013 return false;
2014
2015
2018
2019
2024 return false;
2027
2028
2029
2030 if (OffsetA > OffsetB) {
2031 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2032 return SizeB <= OffDiff;
2033 }
2034 if (OffsetA < OffsetB) {
2035 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2036 return SizeA <= OffDiff;
2037 }
2038
2039 return false;
2040}
2041
2042
2044 int &Value) const {
2046 unsigned BasePos = 0, OffsetPos = 0;
2048 return false;
2050 if (OffsetOp.isImm()) {
2052 return true;
2053 }
2054 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2056 if (AddOp.isImm()) {
2058 return true;
2059 }
2060 }
2061
2062 return false;
2063}
2064
2065std::pair<unsigned, unsigned>
2069}
2070
2073 using namespace HexagonII;
2074
2075 static const std::pair<unsigned, const char*> Flags[] = {
2076 {MO_PCREL, "hexagon-pcrel"},
2077 {MO_GOT, "hexagon-got"},
2078 {MO_LO16, "hexagon-lo16"},
2079 {MO_HI16, "hexagon-hi16"},
2080 {MO_GPREL, "hexagon-gprel"},
2081 {MO_GDGOT, "hexagon-gdgot"},
2082 {MO_GDPLT, "hexagon-gdplt"},
2083 {MO_IE, "hexagon-ie"},
2084 {MO_IEGOT, "hexagon-iegot"},
2085 {MO_TPREL, "hexagon-tprel"}
2086 };
2088}
2089
2092 using namespace HexagonII;
2093
2094 static const std::pair<unsigned, const char*> Flags[] = {
2095 {HMOTF_ConstExtended, "hexagon-ext"}
2096 };
2098}
2099
2103 if (VT == MVT::i1) {
2104 TRC = &Hexagon::PredRegsRegClass;
2105 } else if (VT == MVT::i32 || VT == MVT::f32) {
2106 TRC = &Hexagon::IntRegsRegClass;
2107 } else if (VT == MVT::i64 || VT == MVT::f64) {
2108 TRC = &Hexagon::DoubleRegsRegClass;
2109 } else {
2111 }
2112
2113 Register NewReg = MRI.createVirtualRegister(TRC);
2114 return NewReg;
2115}
2116
2119}
2120
2122 const uint64_t F = MI.getDesc().TSFlags;
2124}
2125
2128}
2129
2132 .getDesc().mayStore() &&
2133 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2134 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2135 (MI) &&
.isBranch() &&
.isReturn() &&
.isCall();
2136}
2137
2138
2141}
2142
2143
2144
2146 const uint64_t F = MI.getDesc().TSFlags;
2148 if (isExtended)
2149 return true;
2150
2154 return false;
2155
2156 if (MI.isCall())
2157 return false;
2158
2161
2162
2164 return true;
2165
2166
2168 return false;
2169
2170
2171
2172
2175 return true;
2176
2177
2178
2179 assert(MO.isImm() && "Extendable operand must be Immediate type");
2180
2183 int32_t SValue = Value;
2186 return SValue < MinValue || SValue > MaxValue;
2187 }
2191 return UValue < MinValue || UValue > MaxValue;
2192}
2193
2195 switch (MI.getOpcode()) {
2196 case Hexagon::L4_return:
2197 case Hexagon::L4_return_t:
2198 case Hexagon::L4_return_f:
2199 case Hexagon::L4_return_tnew_pnt:
2200 case Hexagon::L4_return_fnew_pnt:
2201 case Hexagon::L4_return_tnew_pt:
2202 case Hexagon::L4_return_fnew_pt:
2203 return true;
2204 }
2205 return false;
2206}
2207
2208
2212 return false;
2214
2219
2222
2223 for (auto &RegA : DefsA)
2224 for (auto &RegB : UsesB) {
2225
2226 if (RegA == RegB)
2227 return true;
2228
2229 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2230 return true;
2231
2232 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2233 return true;
2234 }
2235
2236 return false;
2237}
2238
2239
2241 switch (MI.getOpcode()) {
2242 case Hexagon::V6_vL32b_cur_pi:
2243 case Hexagon::V6_vL32b_cur_ai:
2244 return true;
2245 }
2246 return false;
2247}
2248
2249
2250
2253 return true;
2254
2255 return false;
2256}
2257
2258
2264}
2265
2267 return (Opcode == Hexagon::ENDLOOP0 ||
2268 Opcode == Hexagon::ENDLOOP1);
2269}
2270
2272 switch(OpType) {
2279 return true;
2280 default:
2281 return false;
2282 }
2283}
2284
2289 return true;
2290
2291
2292
2293 switch (MI.getOpcode()) {
2294
2295 case Hexagon::PS_fi:
2296 case Hexagon::PS_fia:
2297 return true;
2298 default:
2299 return false;
2300 }
2301 return false;
2302}
2303
2304
2305
2306
2308
2309 const uint64_t F = MI.getDesc().TSFlags;
2311 return true;
2312
2313
2316 return true;
2317 return false;
2318}
2319
2321 unsigned Opcode = MI.getOpcode();
2324}
2325
2326
2330 return false;
2331 if (.mayLoad() &&
.mayStore())
2332 return false;
2334}
2335
2337 switch (MI.getOpcode()) {
2338 case Hexagon::J2_callr:
2339 case Hexagon::J2_callrf:
2340 case Hexagon::J2_callrt:
2341 case Hexagon::PS_call_nr:
2342 return true;
2343 }
2344 return false;
2345}
2346
2348 switch (MI.getOpcode()) {
2349 case Hexagon::L4_return:
2350 case Hexagon::L4_return_t:
2351 case Hexagon::L4_return_f:
2352 case Hexagon::L4_return_fnew_pnt:
2353 case Hexagon::L4_return_fnew_pt:
2354 case Hexagon::L4_return_tnew_pnt:
2355 case Hexagon::L4_return_tnew_pt:
2356 return true;
2357 }
2358 return false;
2359}
2360
2362 switch (MI.getOpcode()) {
2363 case Hexagon::J2_jumpr:
2364 case Hexagon::J2_jumprt:
2365 case Hexagon::J2_jumprf:
2366 case Hexagon::J2_jumprtnewpt:
2367 case Hexagon::J2_jumprfnewpt:
2368 case Hexagon::J2_jumprtnew:
2369 case Hexagon::J2_jumprfnew:
2370 return true;
2371 }
2372 return false;
2373}
2374
2375
2376
2377
2378
2380 unsigned offset) const {
2381
2382
2384 return isInt<11>(offset);
2385
2386 switch (MI.getOpcode()) {
2387
2388 default:
2389 return false;
2390 case Hexagon::J2_jump:
2391 case Hexagon::J2_call:
2392 case Hexagon::PS_call_nr:
2393 return isInt<24>(offset);
2394 case Hexagon::J2_jumpt:
2395 case Hexagon::J2_jumpf:
2396 case Hexagon::J2_jumptnew:
2397 case Hexagon::J2_jumptnewpt:
2398 case Hexagon::J2_jumpfnew:
2399 case Hexagon::J2_jumpfnewpt:
2400 case Hexagon::J2_callt:
2401 case Hexagon::J2_callf:
2402 return isInt<17>(offset);
2403 case Hexagon::J2_loop0i:
2404 case Hexagon::J2_loop0iext:
2405 case Hexagon::J2_loop0r:
2406 case Hexagon::J2_loop0rext:
2407 case Hexagon::J2_loop1i:
2408 case Hexagon::J2_loop1iext:
2409 case Hexagon::J2_loop1r:
2410 case Hexagon::J2_loop1rext:
2411 return isInt<9>(offset);
2412
2413 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2414 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2415 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2416 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2417 return isInt<11>(offset);
2418 }
2419}
2420
2422
2423
2425}
2426
2428 unsigned Opcode = MI.getOpcode();
2429 return Opcode == Hexagon::J2_loop0i ||
2430 Opcode == Hexagon::J2_loop0r ||
2431 Opcode == Hexagon::J2_loop0iext ||
2432 Opcode == Hexagon::J2_loop0rext ||
2433 Opcode == Hexagon::J2_loop1i ||
2434 Opcode == Hexagon::J2_loop1r ||
2435 Opcode == Hexagon::J2_loop1iext ||
2436 Opcode == Hexagon::J2_loop1rext;
2437}
2438
2440 switch (MI.getOpcode()) {
2441 default: return false;
2442 case Hexagon::L4_iadd_memopw_io:
2443 case Hexagon::L4_isub_memopw_io:
2444 case Hexagon::L4_add_memopw_io:
2445 case Hexagon::L4_sub_memopw_io:
2446 case Hexagon::L4_and_memopw_io:
2447 case Hexagon::L4_or_memopw_io:
2448 case Hexagon::L4_iadd_memoph_io:
2449 case Hexagon::L4_isub_memoph_io:
2450 case Hexagon::L4_add_memoph_io:
2451 case Hexagon::L4_sub_memoph_io:
2452 case Hexagon::L4_and_memoph_io:
2453 case Hexagon::L4_or_memoph_io:
2454 case Hexagon::L4_iadd_memopb_io:
2455 case Hexagon::L4_isub_memopb_io:
2456 case Hexagon::L4_add_memopb_io:
2457 case Hexagon::L4_sub_memopb_io:
2458 case Hexagon::L4_and_memopb_io:
2459 case Hexagon::L4_or_memopb_io:
2460 case Hexagon::L4_ior_memopb_io:
2461 case Hexagon::L4_ior_memoph_io:
2462 case Hexagon::L4_ior_memopw_io:
2463 case Hexagon::L4_iand_memopb_io:
2464 case Hexagon::L4_iand_memoph_io:
2465 case Hexagon::L4_iand_memopw_io:
2466 return true;
2467 }
2468 return false;
2469}
2470
2472 const uint64_t F = MI.getDesc().TSFlags;
2474}
2475
2479}
2480
2483}
2484
2487}
2488
2491}
2492
2494 const uint64_t F = MI.getDesc().TSFlags;
2496}
2497
2501}
2502
2503
2505 unsigned OperandNum) const {
2506 const uint64_t F = MI.getDesc().TSFlags;
2508 == OperandNum;
2509}
2510
2512 const uint64_t F = MI.getDesc().TSFlags;
2515}
2516
2521}
2522
2524 const uint64_t F = MI.getDesc().TSFlags;
2527}
2528
2531
2535}
2536
2540}
2541
2545}
2546
2552}
2553
2555 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2556 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2557 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2558 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2559}
2560
2562 switch (MI.getOpcode()) {
2563
2564 case Hexagon::L2_loadrb_io:
2565 case Hexagon::L4_loadrb_ur:
2566 case Hexagon::L4_loadrb_ap:
2567 case Hexagon::L2_loadrb_pr:
2568 case Hexagon::L2_loadrb_pbr:
2569 case Hexagon::L2_loadrb_pi:
2570 case Hexagon::L2_loadrb_pci:
2571 case Hexagon::L2_loadrb_pcr:
2572 case Hexagon::L2_loadbsw2_io:
2573 case Hexagon::L4_loadbsw2_ur:
2574 case Hexagon::L4_loadbsw2_ap:
2575 case Hexagon::L2_loadbsw2_pr:
2576 case Hexagon::L2_loadbsw2_pbr:
2577 case Hexagon::L2_loadbsw2_pi:
2578 case Hexagon::L2_loadbsw2_pci:
2579 case Hexagon::L2_loadbsw2_pcr:
2580 case Hexagon::L2_loadbsw4_io:
2581 case Hexagon::L4_loadbsw4_ur:
2582 case Hexagon::L4_loadbsw4_ap:
2583 case Hexagon::L2_loadbsw4_pr:
2584 case Hexagon::L2_loadbsw4_pbr:
2585 case Hexagon::L2_loadbsw4_pi:
2586 case Hexagon::L2_loadbsw4_pci:
2587 case Hexagon::L2_loadbsw4_pcr:
2588 case Hexagon::L4_loadrb_rr:
2589 case Hexagon::L2_ploadrbt_io:
2590 case Hexagon::L2_ploadrbt_pi:
2591 case Hexagon::L2_ploadrbf_io:
2592 case Hexagon::L2_ploadrbf_pi:
2593 case Hexagon::L2_ploadrbtnew_io:
2594 case Hexagon::L2_ploadrbfnew_io:
2595 case Hexagon::L4_ploadrbt_rr:
2596 case Hexagon::L4_ploadrbf_rr:
2597 case Hexagon::L4_ploadrbtnew_rr:
2598 case Hexagon::L4_ploadrbfnew_rr:
2599 case Hexagon::L2_ploadrbtnew_pi:
2600 case Hexagon::L2_ploadrbfnew_pi:
2601 case Hexagon::L4_ploadrbt_abs:
2602 case Hexagon::L4_ploadrbf_abs:
2603 case Hexagon::L4_ploadrbtnew_abs:
2604 case Hexagon::L4_ploadrbfnew_abs:
2605 case Hexagon::L2_loadrbgp:
2606
2607 case Hexagon::L2_loadrh_io:
2608 case Hexagon::L4_loadrh_ur:
2609 case Hexagon::L4_loadrh_ap:
2610 case Hexagon::L2_loadrh_pr:
2611 case Hexagon::L2_loadrh_pbr:
2612 case Hexagon::L2_loadrh_pi:
2613 case Hexagon::L2_loadrh_pci:
2614 case Hexagon::L2_loadrh_pcr:
2615 case Hexagon::L4_loadrh_rr:
2616 case Hexagon::L2_ploadrht_io:
2617 case Hexagon::L2_ploadrht_pi:
2618 case Hexagon::L2_ploadrhf_io:
2619 case Hexagon::L2_ploadrhf_pi:
2620 case Hexagon::L2_ploadrhtnew_io:
2621 case Hexagon::L2_ploadrhfnew_io:
2622 case Hexagon::L4_ploadrht_rr:
2623 case Hexagon::L4_ploadrhf_rr:
2624 case Hexagon::L4_ploadrhtnew_rr:
2625 case Hexagon::L4_ploadrhfnew_rr:
2626 case Hexagon::L2_ploadrhtnew_pi:
2627 case Hexagon::L2_ploadrhfnew_pi:
2628 case Hexagon::L4_ploadrht_abs:
2629 case Hexagon::L4_ploadrhf_abs:
2630 case Hexagon::L4_ploadrhtnew_abs:
2631 case Hexagon::L4_ploadrhfnew_abs:
2632 case Hexagon::L2_loadrhgp:
2633 return true;
2634 default:
2635 return false;
2636 }
2637}
2638
2640 const uint64_t F = MI.getDesc().TSFlags;
2642}
2643
2645 switch (MI.getOpcode()) {
2646 case Hexagon::STriw_pred:
2647 case Hexagon::LDriw_pred:
2648 return true;
2649 default:
2650 return false;
2651 }
2652}
2653
2655 if (.isBranch())
2656 return false;
2657
2658 for (auto &Op : MI.operands())
2659 if (Op.isGlobal() || Op.isSymbol())
2660 return true;
2661 return false;
2662}
2663
2664
2666 unsigned SchedClass = MI.getDesc().getSchedClass();
2667 return is_TC1(SchedClass);
2668}
2669
2671 unsigned SchedClass = MI.getDesc().getSchedClass();
2672 return is_TC2(SchedClass);
2673}
2674
2676 unsigned SchedClass = MI.getDesc().getSchedClass();
2678}
2679
2681 unsigned SchedClass = MI.getDesc().getSchedClass();
2682 return is_TC4x(SchedClass);
2683}
2684
2685
2689
2692 for (int I = 0; I < N; I++)
2694 return true;
2695 }
2697 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2700 return true;
2701 return false;
2702}
2703
2707}
2708
2709
2713 return false;
2715
2717
2718 case MVT::i8:
2719 case MVT::i16:
2720 case MVT::i32:
2721 case MVT::i64:
2722 case MVT::f32:
2723 case MVT::f64:
2724 case MVT::v2i16:
2725 case MVT::v2i32:
2726 case MVT::v4i8:
2727 case MVT::v4i16:
2728 case MVT::v8i8:
2729 return isInt<4>(Count);
2730
2731 case MVT::v64i8:
2732 case MVT::v32i16:
2733 case MVT::v16i32:
2734 case MVT::v8i64:
2735 case MVT::v128i8:
2736 case MVT::v64i16:
2737 case MVT::v32i32:
2738 case MVT::v16i64:
2739 return isInt<3>(Count);
2740 default:
2741 break;
2742 }
2743
2745}
2746
2749
2750
2751
2752
2753
2754
2755
2756
2757 switch (Opcode) {
2758 case Hexagon::PS_vstorerq_ai:
2759 case Hexagon::PS_vstorerv_ai:
2760 case Hexagon::PS_vstorerw_ai:
2761 case Hexagon::PS_vstorerw_nt_ai:
2762 case Hexagon::PS_vloadrq_ai:
2763 case Hexagon::PS_vloadrv_ai:
2764 case Hexagon::PS_vloadrw_ai:
2765 case Hexagon::PS_vloadrw_nt_ai:
2766 case Hexagon::V6_vL32b_ai:
2767 case Hexagon::V6_vS32b_ai:
2768 case Hexagon::V6_vS32b_pred_ai:
2769 case Hexagon::V6_vS32b_npred_ai:
2770 case Hexagon::V6_vS32b_qpred_ai:
2771 case Hexagon::V6_vS32b_nqpred_ai:
2772 case Hexagon::V6_vS32b_new_ai:
2773 case Hexagon::V6_vS32b_new_pred_ai:
2774 case Hexagon::V6_vS32b_new_npred_ai:
2775 case Hexagon::V6_vS32b_nt_pred_ai:
2776 case Hexagon::V6_vS32b_nt_npred_ai:
2777 case Hexagon::V6_vS32b_nt_new_ai:
2778 case Hexagon::V6_vS32b_nt_new_pred_ai:
2779 case Hexagon::V6_vS32b_nt_new_npred_ai:
2780 case Hexagon::V6_vS32b_nt_qpred_ai:
2781 case Hexagon::V6_vS32b_nt_nqpred_ai:
2782 case Hexagon::V6_vL32b_nt_ai:
2783 case Hexagon::V6_vS32b_nt_ai:
2784 case Hexagon::V6_vL32Ub_ai:
2785 case Hexagon::V6_vS32Ub_ai:
2786 case Hexagon::V6_vL32b_cur_ai:
2787 case Hexagon::V6_vL32b_tmp_ai:
2788 case Hexagon::V6_vL32b_pred_ai:
2789 case Hexagon::V6_vL32b_npred_ai:
2790 case Hexagon::V6_vL32b_cur_pred_ai:
2791 case Hexagon::V6_vL32b_cur_npred_ai:
2792 case Hexagon::V6_vL32b_tmp_pred_ai:
2793 case Hexagon::V6_vL32b_tmp_npred_ai:
2794 case Hexagon::V6_vL32b_nt_cur_ai:
2795 case Hexagon::V6_vL32b_nt_tmp_ai:
2796 case Hexagon::V6_vL32b_nt_pred_ai:
2797 case Hexagon::V6_vL32b_nt_npred_ai:
2798 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2799 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2800 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2801 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2802 case Hexagon::V6_vgathermh_pseudo:
2803 case Hexagon::V6_vgathermw_pseudo:
2804 case Hexagon::V6_vgathermhw_pseudo:
2805 case Hexagon::V6_vgathermhq_pseudo:
2806 case Hexagon::V6_vgathermwq_pseudo:
2807 case Hexagon::V6_vgathermhwq_pseudo: {
2808 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2810 if (Offset & (VectorSize-1))
2811 return false;
2813 }
2814
2815 case Hexagon::J2_loop0i:
2816 case Hexagon::J2_loop1i:
2817 return isUInt<10>(Offset);
2818
2819 case Hexagon::S4_storeirb_io:
2820 case Hexagon::S4_storeirbt_io:
2821 case Hexagon::S4_storeirbf_io:
2822 return isUInt<6>(Offset);
2823
2824 case Hexagon::S4_storeirh_io:
2825 case Hexagon::S4_storeirht_io:
2826 case Hexagon::S4_storeirhf_io:
2827 return isShiftedUInt<6,1>(Offset);
2828
2829 case Hexagon::S4_storeiri_io:
2830 case Hexagon::S4_storeirit_io:
2831 case Hexagon::S4_storeirif_io:
2832 return isShiftedUInt<6,2>(Offset);
2833
2834 case Hexagon::A4_cmpbeqi:
2835 return isUInt<8>(Offset);
2836 case Hexagon::A4_cmpbgti:
2837 return isInt<8>(Offset);
2838 }
2839
2840 if (Extend)
2841 return true;
2842
2843 switch (Opcode) {
2844 case Hexagon::L2_loadri_io:
2845 case Hexagon::S2_storeri_io:
2848
2849 case Hexagon::L2_loadrd_io:
2850 case Hexagon::S2_storerd_io:
2853
2854 case Hexagon::L2_loadrh_io:
2855 case Hexagon::L2_loadruh_io:
2856 case Hexagon::S2_storerh_io:
2857 case Hexagon::S2_storerf_io:
2860
2861 case Hexagon::L2_loadrb_io:
2862 case Hexagon::L2_loadrub_io:
2863 case Hexagon::S2_storerb_io:
2866
2867 case Hexagon::A2_addi:
2870
2871 case Hexagon::L4_iadd_memopw_io:
2872 case Hexagon::L4_isub_memopw_io:
2873 case Hexagon::L4_add_memopw_io:
2874 case Hexagon::L4_sub_memopw_io:
2875 case Hexagon::L4_iand_memopw_io:
2876 case Hexagon::L4_ior_memopw_io:
2877 case Hexagon::L4_and_memopw_io:
2878 case Hexagon::L4_or_memopw_io:
2880
2881 case Hexagon::L4_iadd_memoph_io:
2882 case Hexagon::L4_isub_memoph_io:
2883 case Hexagon::L4_add_memoph_io:
2884 case Hexagon::L4_sub_memoph_io:
2885 case Hexagon::L4_iand_memoph_io:
2886 case Hexagon::L4_ior_memoph_io:
2887 case Hexagon::L4_and_memoph_io:
2888 case Hexagon::L4_or_memoph_io:
2890
2891 case Hexagon::L4_iadd_memopb_io:
2892 case Hexagon::L4_isub_memopb_io:
2893 case Hexagon::L4_add_memopb_io:
2894 case Hexagon::L4_sub_memopb_io:
2895 case Hexagon::L4_iand_memopb_io:
2896 case Hexagon::L4_ior_memopb_io:
2897 case Hexagon::L4_and_memopb_io:
2898 case Hexagon::L4_or_memopb_io:
2900
2901
2902
2903 case Hexagon::STriw_pred:
2904 case Hexagon::LDriw_pred:
2905 case Hexagon::STriw_ctr:
2906 case Hexagon::LDriw_ctr:
2907 return true;
2908
2909 case Hexagon::PS_fi:
2910 case Hexagon::PS_fia:
2911 case Hexagon::INLINEASM:
2912 return true;
2913
2914 case Hexagon::L2_ploadrbt_io:
2915 case Hexagon::L2_ploadrbf_io:
2916 case Hexagon::L2_ploadrubt_io:
2917 case Hexagon::L2_ploadrubf_io:
2918 case Hexagon::S2_pstorerbt_io:
2919 case Hexagon::S2_pstorerbf_io:
2920 return isUInt<6>(Offset);
2921
2922 case Hexagon::L2_ploadrht_io:
2923 case Hexagon::L2_ploadrhf_io:
2924 case Hexagon::L2_ploadruht_io:
2925 case Hexagon::L2_ploadruhf_io:
2926 case Hexagon::S2_pstorerht_io:
2927 case Hexagon::S2_pstorerhf_io:
2928 return isShiftedUInt<6,1>(Offset);
2929
2930 case Hexagon::L2_ploadrit_io:
2931 case Hexagon::L2_ploadrif_io:
2932 case Hexagon::S2_pstorerit_io:
2933 case Hexagon::S2_pstorerif_io:
2934 return isShiftedUInt<6,2>(Offset);
2935
2936 case Hexagon::L2_ploadrdt_io:
2937 case Hexagon::L2_ploadrdf_io:
2938 case Hexagon::S2_pstorerdt_io:
2939 case Hexagon::S2_pstorerdf_io:
2940 return isShiftedUInt<6,3>(Offset);
2941
2942 case Hexagon::L2_loadbsw2_io:
2943 case Hexagon::L2_loadbzw2_io:
2944 return isShiftedInt<11,1>(Offset);
2945
2946 case Hexagon::L2_loadbsw4_io:
2947 case Hexagon::L2_loadbzw4_io:
2948 return isShiftedInt<11,2>(Offset);
2949 }
2950
2951 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2952 << ")\n";
2953 llvm_unreachable("No offset range is defined for this opcode. "
2954 "Please define it in the above switch statement!");
2955}
2956
2959}
2960
2964 return
2967}
2968
2972 return true;
2973
2975 return true;
2976
2978 return true;
2979
2980 return false;
2981}
2982
2984 switch (MI.getOpcode()) {
2985
2986 case Hexagon::L2_loadrub_io:
2987 case Hexagon::L4_loadrub_ur:
2988 case Hexagon::L4_loadrub_ap:
2989 case Hexagon::L2_loadrub_pr:
2990 case Hexagon::L2_loadrub_pbr:
2991 case Hexagon::L2_loadrub_pi:
2992 case Hexagon::L2_loadrub_pci:
2993 case Hexagon::L2_loadrub_pcr:
2994 case Hexagon::L2_loadbzw2_io:
2995 case Hexagon::L4_loadbzw2_ur:
2996 case Hexagon::L4_loadbzw2_ap:
2997 case Hexagon::L2_loadbzw2_pr:
2998 case Hexagon::L2_loadbzw2_pbr:
2999 case Hexagon::L2_loadbzw2_pi:
3000 case Hexagon::L2_loadbzw2_pci:
3001 case Hexagon::L2_loadbzw2_pcr:
3002 case Hexagon::L2_loadbzw4_io:
3003 case Hexagon::L4_loadbzw4_ur:
3004 case Hexagon::L4_loadbzw4_ap:
3005 case Hexagon::L2_loadbzw4_pr:
3006 case Hexagon::L2_loadbzw4_pbr:
3007 case Hexagon::L2_loadbzw4_pi:
3008 case Hexagon::L2_loadbzw4_pci:
3009 case Hexagon::L2_loadbzw4_pcr:
3010 case Hexagon::L4_loadrub_rr:
3011 case Hexagon::L2_ploadrubt_io:
3012 case Hexagon::L2_ploadrubt_pi:
3013 case Hexagon::L2_ploadrubf_io:
3014 case Hexagon::L2_ploadrubf_pi:
3015 case Hexagon::L2_ploadrubtnew_io:
3016 case Hexagon::L2_ploadrubfnew_io:
3017 case Hexagon::L4_ploadrubt_rr:
3018 case Hexagon::L4_ploadrubf_rr:
3019 case Hexagon::L4_ploadrubtnew_rr:
3020 case Hexagon::L4_ploadrubfnew_rr:
3021 case Hexagon::L2_ploadrubtnew_pi:
3022 case Hexagon::L2_ploadrubfnew_pi:
3023 case Hexagon::L4_ploadrubt_abs:
3024 case Hexagon::L4_ploadrubf_abs:
3025 case Hexagon::L4_ploadrubtnew_abs:
3026 case Hexagon::L4_ploadrubfnew_abs:
3027 case Hexagon::L2_loadrubgp:
3028
3029 case Hexagon::L2_loadruh_io:
3030 case Hexagon::L4_loadruh_ur:
3031 case Hexagon::L4_loadruh_ap:
3032 case Hexagon::L2_loadruh_pr:
3033 case Hexagon::L2_loadruh_pbr:
3034 case Hexagon::L2_loadruh_pi:
3035 case Hexagon::L2_loadruh_pci:
3036 case Hexagon::L2_loadruh_pcr:
3037 case Hexagon::L4_loadruh_rr:
3038 case Hexagon::L2_ploadruht_io:
3039 case Hexagon::L2_ploadruht_pi:
3040 case Hexagon::L2_ploadruhf_io:
3041 case Hexagon::L2_ploadruhf_pi:
3042 case Hexagon::L2_ploadruhtnew_io:
3043 case Hexagon::L2_ploadruhfnew_io:
3044 case Hexagon::L4_ploadruht_rr:
3045 case Hexagon::L4_ploadruhf_rr:
3046 case Hexagon::L4_ploadruhtnew_rr:
3047 case Hexagon::L4_ploadruhfnew_rr:
3048 case Hexagon::L2_ploadruhtnew_pi:
3049 case Hexagon::L2_ploadruhfnew_pi:
3050 case Hexagon::L4_ploadruht_abs:
3051 case Hexagon::L4_ploadruhf_abs:
3052 case Hexagon::L4_ploadruhtnew_abs:
3053 case Hexagon::L4_ploadruhfnew_abs:
3054 case Hexagon::L2_loadruhgp:
3055 return true;
3056 default:
3057 return false;
3058 }
3059}
3060
3061
3066 return true;
3067 return false;
3068}
3069
3070
3075 OffsetIsScalable = false;
3077 if (!BaseOp || !BaseOp->isReg())
3078 return false;
3080 return true;
3081}
3082
3083
3086 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3088 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3089 return true;
3090 }
3092 return false;
3094
3095
3098 if (!Stored.isReg())
3099 return false;
3100 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3102 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3103 return true;
3104 }
3105 }
3106 return false;
3107}
3108
3110 unsigned Opc = CallMI.getOpcode();
3111 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3112}
3113
3116 if (I.isEHLabel())
3117 return true;
3118 return false;
3119}
3120
3121
3122
3124 short NonExtOpcode;
3125
3126
3127 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3128 return true;
3129
3130 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3131
3132
3135
3136
3137 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3138 break;
3140
3141
3142
3143 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3144 break;
3146 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3147 break;
3148 default:
3149 return false;
3150 }
3151 if (NonExtOpcode < 0)
3152 return false;
3153 return true;
3154 }
3155 return false;
3156}
3157
3159 return Hexagon::getRealHWInstr(MI.getOpcode(),
3160 Hexagon::InstrType_Pseudo) >= 0;
3161}
3162
3164 const {
3166 while (I != E) {
3167 if (I->isBarrier())
3168 return true;
3169 ++I;
3170 }
3171 return false;
3172}
3173
3174
3176 const uint64_t F = MI.getDesc().TSFlags;
3179}
3180
3181
3184 return false;
3185
3186 const uint64_t F = MI.getDesc().TSFlags;
3188}
3189
3192
3194 return false;
3195
3196
3198 return false;
3199
3200
3201
3203 return false;
3204
3205 return true;
3206}
3207
3210
3212 return false;
3213
3216
3217 if (!MII->isBundle())
3219
3220 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3223 return true;
3224 }
3225 return false;
3226}
3227
3231
3232 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3233 return false;
3234 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3235 return false;
3236 }
3237
3238
3239
3240 switch (MI.getOpcode()) {
3241 case Hexagon::A4_addp_c:
3242 case Hexagon::A4_subp_c:
3243 case Hexagon::A4_tlbmatch:
3244 case Hexagon::A5_ACS:
3245 case Hexagon::F2_sfinvsqrta:
3246 case Hexagon::F2_sfrecipa:
3247 case Hexagon::J2_endloop0:
3248 case Hexagon::J2_endloop01:
3249 case Hexagon::J2_ploop1si:
3250 case Hexagon::J2_ploop1sr:
3251 case Hexagon::J2_ploop2si:
3252 case Hexagon::J2_ploop2sr:
3253 case Hexagon::J2_ploop3si:
3254 case Hexagon::J2_ploop3sr:
3255 case Hexagon::S2_cabacdecbin:
3256 case Hexagon::S2_storew_locked:
3257 case Hexagon::S4_stored_locked:
3258 return false;
3259 }
3260 return true;
3261}
3262
3264 return Opcode == Hexagon::J2_jumpt ||
3265 Opcode == Hexagon::J2_jumptpt ||
3266 Opcode == Hexagon::J2_jumpf ||
3267 Opcode == Hexagon::J2_jumpfpt ||
3268 Opcode == Hexagon::J2_jumptnew ||
3269 Opcode == Hexagon::J2_jumpfnew ||
3270 Opcode == Hexagon::J2_jumptnewpt ||
3271 Opcode == Hexagon::J2_jumpfnewpt;
3272}
3273
3276 return false;
3278}
3279
3281 const uint64_t F = MI.getDesc().TSFlags;
3283}
3284
3285
3286
3287
3288
3292
3296 return nullptr;
3297
3299
3300 unsigned BasePos = 0, OffsetPos = 0;
3302 return nullptr;
3303
3304
3305
3308 } else {
3310 if (!OffsetOp.isImm())
3311 return nullptr;
3313 }
3314
3317 return nullptr;
3319}
3320
3321
3323 unsigned &BasePos, unsigned &OffsetPos) const {
3325 return false;
3326
3327
3329 BasePos = 0;
3330 OffsetPos = 1;
3331 } else if (MI.mayStore()) {
3332 BasePos = 0;
3333 OffsetPos = 1;
3334 } else if (MI.mayLoad()) {
3335 BasePos = 1;
3336 OffsetPos = 2;
3337 } else
3338 return false;
3339
3341 BasePos++;
3342 OffsetPos++;
3343 }
3345 BasePos++;
3346 OffsetPos++;
3347 }
3348
3349 if (.getOperand(BasePos).isReg() ||
.getOperand(OffsetPos).isImm())
3350 return false;
3351
3352 return true;
3353}
3354
3355
3356
3357
3358
3362
3365 return Jumpers;
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379 do {
3380 --I;
3381 if (I->isEHLabel())
3382 return Jumpers;
3384
3386 --I;
3387
3388 while (I->isDebugInstr()) {
3390 return Jumpers;
3391 --I;
3392 }
3393 if (!isUnpredicatedTerminator(*I))
3394 return Jumpers;
3395
3396
3400
3401 do {
3402 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
3403 if (!SecondLastInst) {
3404 SecondLastInst = &*I;
3405 Jumpers.push_back(SecondLastInst);
3406 } else
3407 return Jumpers;
3408 }
3410 break;
3411 --I;
3412 } while (true);
3413 return Jumpers;
3414}
3415
3416
3418 const uint64_t F = MI.getDesc().TSFlags;
3420}
3421
3422
3423
3426 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3427
3428 switch (MI.getOpcode()) {
3429 default:
3431
3432
3433
3434
3435
3436
3437 case Hexagon::C2_cmpeq:
3438 case Hexagon::C2_cmpgt:
3439 case Hexagon::C2_cmpgtu:
3440 DstReg = MI.getOperand(0).getReg();
3441 Src1Reg = MI.getOperand(1).getReg();
3442 Src2Reg = MI.getOperand(2).getReg();
3443 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3444 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3447 break;
3448 case Hexagon::C2_cmpeqi:
3449 case Hexagon::C2_cmpgti:
3450 case Hexagon::C2_cmpgtui:
3451
3452 DstReg = MI.getOperand(0).getReg();
3453 SrcReg = MI.getOperand(1).getReg();
3454 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3455 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3457 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3458 (MI.getOperand(2).getImm() == -1)))
3460 break;
3461 case Hexagon::A2_tfr:
3462
3463 DstReg = MI.getOperand(0).getReg();
3464 SrcReg = MI.getOperand(1).getReg();
3467 break;
3468 case Hexagon::A2_tfrsi:
3469
3470
3471
3472 DstReg = MI.getOperand(0).getReg();
3475 break;
3476 case Hexagon::S2_tstbit_i:
3477 DstReg = MI.getOperand(0).getReg();
3478 Src1Reg = MI.getOperand(1).getReg();
3479 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3480 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3481 MI.getOperand(2).isImm() &&
3484 break;
3485
3486
3487
3488
3489 case Hexagon::J2_jumptnew:
3490 case Hexagon::J2_jumpfnew:
3491 case Hexagon::J2_jumptnewpt:
3492 case Hexagon::J2_jumpfnewpt:
3493 Src1Reg = MI.getOperand(0).getReg();
3494 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3495 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3497 break;
3498
3499
3500
3501
3502 case Hexagon::J2_jump:
3503 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3504 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3506 }
3507
3509}
3510
3511
3516 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3517 (GB.getOpcode() != Hexagon::J2_jumptnew))
3518 return -1u;
3520 if (!GB.readsRegister(DestReg, nullptr))
3521 return -1u;
3522 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3523 return -1u;
3524
3526 if (!CmpOp.isImm())
3527 return -1u;
3528 int V = CmpOp.getImm();
3529 if (V == -1)
3530 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3531 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3532 if (!isUInt<5>(V))
3533 return -1u;
3534 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3535 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3536}
3537
3538
3540 bool ForBigCore) const {
3541
3542
3543
3544
3545
3546
3547
3548 static const std::map<unsigned, unsigned> DupMap = {
3549 {Hexagon::A2_add, Hexagon::dup_A2_add},
3550 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3551 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3552 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3553 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3554 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3555 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3556 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3557 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3558 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3559 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3560 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3561 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3562 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3563 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3564 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3565 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3566 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3567 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3568 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3569 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3570 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3571 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3572 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3573 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3574 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3575 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3576 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3577 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3578 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3579 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3580 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3581 };
3582 unsigned OpNum = MI.getOpcode();
3583
3584 if (ForBigCore) {
3585 auto Iter = DupMap.find(OpNum);
3586 if (Iter != DupMap.end())
3587 return Iter->second;
3588 } else {
3589 for (const auto &Iter : DupMap)
3590 if (Iter.second == OpNum)
3591 return Iter.first;
3592 }
3593 return -1;
3594}
3595
3597 enum Hexagon::PredSense inPredSense;
3598 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3599 Hexagon::PredSense_true;
3600 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3601 if (CondOpcode >= 0)
3602 return CondOpcode;
3603
3605}
3606
3607
3609 switch (MI.getOpcode()) {
3611 case Hexagon::V6_vL32b_pi:
3612 return Hexagon::V6_vL32b_cur_pi;
3613 case Hexagon::V6_vL32b_ai:
3614 return Hexagon::V6_vL32b_cur_ai;
3615 case Hexagon::V6_vL32b_nt_pi:
3616 return Hexagon::V6_vL32b_nt_cur_pi;
3617 case Hexagon::V6_vL32b_nt_ai:
3618 return Hexagon::V6_vL32b_nt_cur_ai;
3619 case Hexagon::V6_vL32b_ppu:
3620 return Hexagon::V6_vL32b_cur_ppu;
3621 case Hexagon::V6_vL32b_nt_ppu:
3622 return Hexagon::V6_vL32b_nt_cur_ppu;
3623 }
3624 return 0;
3625}
3626
3627
3629 switch (MI.getOpcode()) {
3631 case Hexagon::V6_vL32b_cur_pi:
3632 return Hexagon::V6_vL32b_pi;
3633 case Hexagon::V6_vL32b_cur_ai:
3634 return Hexagon::V6_vL32b_ai;
3635 case Hexagon::V6_vL32b_nt_cur_pi:
3636 return Hexagon::V6_vL32b_nt_pi;
3637 case Hexagon::V6_vL32b_nt_cur_ai:
3638 return Hexagon::V6_vL32b_nt_ai;
3639 case Hexagon::V6_vL32b_cur_ppu:
3640 return Hexagon::V6_vL32b_ppu;
3641 case Hexagon::V6_vL32b_nt_cur_ppu:
3642 return Hexagon::V6_vL32b_nt_ppu;
3643 }
3644 return 0;
3645}
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3730 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3731 if (NVOpcode >= 0)
3732 return NVOpcode;
3733
3734 switch (MI.getOpcode()) {
3735 default:
3737 std::to_string(MI.getOpcode()));
3738 case Hexagon::S4_storerb_ur:
3739 return Hexagon::S4_storerbnew_ur;
3740
3741 case Hexagon::S2_storerb_pci:
3742 return Hexagon::S2_storerb_pci;
3743
3744 case Hexagon::S2_storeri_pci:
3745 return Hexagon::S2_storeri_pci;
3746
3747 case Hexagon::S2_storerh_pci:
3748 return Hexagon::S2_storerh_pci;
3749
3750 case Hexagon::S2_storerd_pci:
3751 return Hexagon::S2_storerd_pci;
3752
3753 case Hexagon::S2_storerf_pci:
3754 return Hexagon::S2_storerf_pci;
3755
3756 case Hexagon::V6_vS32b_ai:
3757 return Hexagon::V6_vS32b_new_ai;
3758
3759 case Hexagon::V6_vS32b_pi:
3760 return Hexagon::V6_vS32b_new_pi;
3761 }
3762 return 0;
3763}
3764
3765
3766
3767
3768
3769
3772
3775 bool Taken = false;
3777
3780 if (MBPI)
3783 };
3784
3785 if (BrTarget.isMBB()) {
3787 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3788 } else {
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798 assert(MI.isConditionalBranch());
3800 bool SawCond = false, Bad = false;
3802 if (.isBranch())
3803 continue;
3804 if (I.isConditionalBranch()) {
3805 SawCond = true;
3807 Bad = true;
3808 break;
3809 }
3810 }
3811 if (I.isUnconditionalBranch() && !SawCond) {
3812 Bad = true;
3813 break;
3814 }
3815 }
3816 if (!Bad) {
3819 if (NextIt == B.instr_end()) {
3820
3822 if (.isLayoutSuccessor(SB))
3823 continue;
3824 Taken = getEdgeProbability(Src, SB) < OneHalf;
3825 break;
3826 }
3827 } else {
3828 assert(NextIt->isUnconditionalBranch());
3829
3832 if (.isMBB())
3833 continue;
3835 break;
3836 }
3837 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3838 }
3839 }
3840 }
3841
3842
3843
3844 switch (MI.getOpcode()) {
3845 case Hexagon::J2_jumpt:
3846 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3847 case Hexagon::J2_jumpf:
3848 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3849
3850 default:
3852 }
3853}
3854
3855
3858 switch (MI.getOpcode()) {
3859
3860 case Hexagon::J2_jumpt:
3861 case Hexagon::J2_jumpf:
3863 }
3864
3865 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3866 if (NewOpcode >= 0)
3867 return NewOpcode;
3868 return 0;
3869}
3870
3872 int NewOp = MI.getOpcode();
3874 NewOp = Hexagon::getPredOldOpcode(NewOp);
3875
3876
3877
3878 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3879 switch (NewOp) {
3880 case Hexagon::J2_jumptpt:
3881 NewOp = Hexagon::J2_jumpt;
3882 break;
3883 case Hexagon::J2_jumpfpt:
3884 NewOp = Hexagon::J2_jumpf;
3885 break;
3886 case Hexagon::J2_jumprtpt:
3887 NewOp = Hexagon::J2_jumprt;
3888 break;
3889 case Hexagon::J2_jumprfpt:
3890 NewOp = Hexagon::J2_jumprf;
3891 break;
3892 }
3893 }
3894 assert(NewOp >= 0 &&
3895 "Couldn't change predicate new instruction to its old form.");
3896 }
3897
3898 if (isNewValueStore(NewOp)) {
3899 NewOp = Hexagon::getNonNVStore(NewOp);
3900 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3901 }
3902
3904 return NewOp;
3905
3906
3907 switch (NewOp) {
3908 case Hexagon::J2_jumpfpt:
3909 return Hexagon::J2_jumpf;
3910 case Hexagon::J2_jumptpt:
3911 return Hexagon::J2_jumpt;
3912 case Hexagon::J2_jumprfpt:
3913 return Hexagon::J2_jumprf;
3914 case Hexagon::J2_jumprtpt:
3915 return Hexagon::J2_jumprt;
3916 }
3917 return NewOp;
3918}
3919
3920
3921
3924 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3926
3927 switch (MI.getOpcode()) {
3928 default:
3930
3931
3932
3933
3934
3935 case Hexagon::L2_loadri_io:
3936 case Hexagon::dup_L2_loadri_io:
3937 DstReg = MI.getOperand(0).getReg();
3938 SrcReg = MI.getOperand(1).getReg();
3939
3940
3942 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3944 MI.getOperand(2).isImm() &&
3945 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3947
3949 (MI.getOperand(2).isImm() &&
3950 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3952 }
3953 break;
3954 case Hexagon::L2_loadrub_io:
3955 case Hexagon::dup_L2_loadrub_io:
3956
3957 DstReg = MI.getOperand(0).getReg();
3958 SrcReg = MI.getOperand(1).getReg();
3960 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3962 break;
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973 case Hexagon::L2_loadrh_io:
3974 case Hexagon::L2_loadruh_io:
3975 case Hexagon::dup_L2_loadrh_io:
3976 case Hexagon::dup_L2_loadruh_io:
3977
3978 DstReg = MI.getOperand(0).getReg();
3979 SrcReg = MI.getOperand(1).getReg();
3981 MI.getOperand(2).isImm() &&
3982 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3984 break;
3985 case Hexagon::L2_loadrb_io:
3986 case Hexagon::dup_L2_loadrb_io:
3987
3988 DstReg = MI.getOperand(0).getReg();
3989 SrcReg = MI.getOperand(1).getReg();
3991 MI.getOperand(2).isImm() &&
3992 isUInt<3>(MI.getOperand(2).getImm()))
3994 break;
3995 case Hexagon::L2_loadrd_io:
3996 case Hexagon::dup_L2_loadrd_io:
3997
3998 DstReg = MI.getOperand(0).getReg();
3999 SrcReg = MI.getOperand(1).getReg();
4001 Hexagon::IntRegsRegClass.contains(SrcReg) &&
4003 MI.getOperand(2).isImm() &&
4004 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4006 break;
4007
4008
4009 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4010 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4011 case Hexagon::L4_return:
4012 case Hexagon::L2_deallocframe:
4013 case Hexagon::dup_L2_deallocframe:
4015 case Hexagon::EH_RETURN_JMPR:
4016 case Hexagon::PS_jmpret:
4017 case Hexagon::SL2_jumpr31:
4018
4019
4020 DstReg = MI.getOperand(0).getReg();
4021 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4023 break;
4024 case Hexagon::PS_jmprett:
4025 case Hexagon::PS_jmpretf:
4026 case Hexagon::PS_jmprettnewpt:
4027 case Hexagon::PS_jmpretfnewpt:
4028 case Hexagon::PS_jmprettnew:
4029 case Hexagon::PS_jmpretfnew:
4030 case Hexagon::SL2_jumpr31_t:
4031 case Hexagon::SL2_jumpr31_f:
4032 case Hexagon::SL2_jumpr31_tnew:
4033 case Hexagon::SL2_jumpr31_fnew:
4034 DstReg = MI.getOperand(1).getReg();
4035 SrcReg = MI.getOperand(0).getReg();
4036
4037 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4038 (Hexagon::P0 == SrcReg)) &&
4039 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4041 break;
4042 case Hexagon::L4_return_t:
4043 case Hexagon::L4_return_f:
4044 case Hexagon::L4_return_tnew_pnt:
4045 case Hexagon::L4_return_fnew_pnt:
4046 case Hexagon::L4_return_tnew_pt:
4047 case Hexagon::L4_return_fnew_pt:
4048
4049 SrcReg = MI.getOperand(0).getReg();
4050 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4052 break;
4053
4054
4055
4056
4057
4058 case Hexagon::S2_storeri_io:
4059 case Hexagon::dup_S2_storeri_io:
4060
4061
4062 Src1Reg = MI.getOperand(0).getReg();
4063 Src2Reg = MI.getOperand(2).getReg();
4064 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4067 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4069
4071 MI.getOperand(1).isImm() &&
4072 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4074 break;
4075 case Hexagon::S2_storerb_io:
4076 case Hexagon::dup_S2_storerb_io:
4077
4078 Src1Reg = MI.getOperand(0).getReg();
4079 Src2Reg = MI.getOperand(2).getReg();
4081 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4083 break;
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093 case Hexagon::S2_storerh_io:
4094 case Hexagon::dup_S2_storerh_io:
4095
4096 Src1Reg = MI.getOperand(0).getReg();
4097 Src2Reg = MI.getOperand(2).getReg();
4099 MI.getOperand(1).isImm() &&
4100 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4102 break;
4103 case Hexagon::S2_storerd_io:
4104 case Hexagon::dup_S2_storerd_io:
4105
4106 Src1Reg = MI.getOperand(0).getReg();
4107 Src2Reg = MI.getOperand(2).getReg();
4109 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4111 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4113 break;
4114 case Hexagon::S4_storeiri_io:
4115 case Hexagon::dup_S4_storeiri_io:
4116
4117 Src1Reg = MI.getOperand(0).getReg();
4119 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4120 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4122 break;
4123 case Hexagon::S4_storeirb_io:
4124 case Hexagon::dup_S4_storeirb_io:
4125
4126 Src1Reg = MI.getOperand(0).getReg();
4128 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4129 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4131 break;
4132 case Hexagon::S2_allocframe:
4133 case Hexagon::dup_S2_allocframe:
4134 if (MI.getOperand(2).isImm() &&
4135 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4137 break;
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156 case Hexagon::A2_addi:
4157 case Hexagon::dup_A2_addi:
4158 DstReg = MI.getOperand(0).getReg();
4159 SrcReg = MI.getOperand(1).getReg();
4161
4162 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4164 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4166
4167 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4168 isInt<7>(MI.getOperand(2).getImm()))
4170
4171
4173 ((MI.getOperand(2).getImm() == 1) ||
4174 (MI.getOperand(2).getImm() == -1)))
4176 }
4177 break;
4178 case Hexagon::A2_add:
4179 case Hexagon::dup_A2_add:
4180
4181 DstReg = MI.getOperand(0).getReg();
4182 Src1Reg = MI.getOperand(1).getReg();
4183 Src2Reg = MI.getOperand(2).getReg();
4187 break;
4188 case Hexagon::A2_andir:
4189 case Hexagon::dup_A2_andir:
4190
4191
4192
4193 DstReg = MI.getOperand(0).getReg();
4194 SrcReg = MI.getOperand(1).getReg();
4196 MI.getOperand(2).isImm() &&
4197 ((MI.getOperand(2).getImm() == 1) ||
4198 (MI.getOperand(2).getImm() == 255)))
4200 break;
4201 case Hexagon::A2_tfr:
4202 case Hexagon::dup_A2_tfr:
4203
4204 DstReg = MI.getOperand(0).getReg();
4205 SrcReg = MI.getOperand(1).getReg();
4208 break;
4209 case Hexagon::A2_tfrsi:
4210 case Hexagon::dup_A2_tfrsi:
4211
4212
4213
4214
4215 DstReg = MI.getOperand(0).getReg();
4218 break;
4219 case Hexagon::C2_cmoveit:
4220 case Hexagon::C2_cmovenewit:
4221 case Hexagon::C2_cmoveif:
4222 case Hexagon::C2_cmovenewif:
4223 case Hexagon::dup_C2_cmoveit:
4224 case Hexagon::dup_C2_cmovenewit:
4225 case Hexagon::dup_C2_cmoveif:
4226 case Hexagon::dup_C2_cmovenewif:
4227
4228
4229
4230 DstReg = MI.getOperand(0).getReg();
4231 SrcReg = MI.getOperand(1).getReg();
4233 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4234 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4236 break;
4237 case Hexagon::C2_cmpeqi:
4238 case Hexagon::dup_C2_cmpeqi:
4239
4240 DstReg = MI.getOperand(0).getReg();
4241 SrcReg = MI.getOperand(1).getReg();
4242 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4244 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4246 break;
4247 case Hexagon::A2_combineii:
4248 case Hexagon::A4_combineii:
4249 case Hexagon::dup_A2_combineii:
4250 case Hexagon::dup_A4_combineii:
4251
4252 DstReg = MI.getOperand(0).getReg();
4254 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4255 (MI.getOperand(1).isGlobal() &&
4256 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4257 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4258 (MI.getOperand(2).isGlobal() &&
4259 isUInt<2>(MI.getOperand(2).getOffset()))))
4261 break;
4262 case Hexagon::A4_combineri:
4263 case Hexagon::dup_A4_combineri:
4264
4265
4266 DstReg = MI.getOperand(0).getReg();
4267 SrcReg = MI.getOperand(1).getReg();
4269 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4270 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4272 break;
4273 case Hexagon::A4_combineir:
4274 case Hexagon::dup_A4_combineir:
4275
4276 DstReg = MI.getOperand(0).getReg();
4277 SrcReg = MI.getOperand(2).getReg();
4279 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4280 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4282 break;
4283 case Hexagon::A2_sxtb:
4284 case Hexagon::A2_sxth:
4285 case Hexagon::A2_zxtb:
4286 case Hexagon::A2_zxth:
4287 case Hexagon::dup_A2_sxtb:
4288 case Hexagon::dup_A2_sxth:
4289 case Hexagon::dup_A2_zxtb:
4290 case Hexagon::dup_A2_zxth:
4291
4292 DstReg = MI.getOperand(0).getReg();
4293 SrcReg = MI.getOperand(1).getReg();
4296 break;
4297 }
4298
4300}
4301
4303 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4304}
4305
4308
4309
4310 if (!ItinData)
4312
4313 if (MI.isTransient())
4314 return 0;
4316}
4317
4318
4319
4320
4321
4322
4323
4324
4325
4328 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4330
4331
4333
4337 int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false);
4338 if (Idx != -1) {
4339 DefIdx = Idx;
4340 break;
4341 }
4342 }
4343 }
4344
4348 int Idx = UseMI.findRegisterUseOperandIdx(SR, &HRI, false);
4349 if (Idx != -1) {
4350 UseIdx = Idx;
4351 break;
4352 }
4353 }
4354 }
4355 }
4356
4358 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4360
4361
4362
4365}
4366
4367
4368
4369
4372 if (Cond.empty())
4373 return false;
4375 Cond[0].setImm(Opc);
4376 return true;
4377}
4378
4380 int InvPredOpcode;
4381 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4382 : Hexagon::getTruePredOpcode(Opc);
4383 if (InvPredOpcode >= 0)
4384 return InvPredOpcode;
4385
4387}
4388
4389
4391 const uint64_t F = MI.getDesc().TSFlags;
4396
4397 if (isSigned)
4398 return ~(-1U << (bits - 1));
4399 else
4400 return ~(-1U << bits);
4401}
4402
4403
4405 switch (MI.getOpcode()) {
4406 case Hexagon::L2_loadrbgp:
4407 case Hexagon::L2_loadrdgp:
4408 case Hexagon::L2_loadrhgp:
4409 case Hexagon::L2_loadrigp:
4410 case Hexagon::L2_loadrubgp:
4411 case Hexagon::L2_loadruhgp:
4412 case Hexagon::S2_storerbgp:
4413 case Hexagon::S2_storerbnewgp:
4414 case Hexagon::S2_storerhgp:
4415 case Hexagon::S2_storerhnewgp:
4416 case Hexagon::S2_storerigp:
4417 case Hexagon::S2_storerinewgp:
4418 case Hexagon::S2_storerdgp:
4419 case Hexagon::S2_storerfgp:
4420 return true;
4421 }
4422 const uint64_t F = MI.getDesc().TSFlags;
4423 unsigned addrMode =
4425
4426
4430}
4431
4433
4434
4435
4436
4437 if (MI.getOpcode() == Hexagon::A4_ext)
4438 return false;
4439
4442}
4443
4445 const uint64_t F = MI.getDesc().TSFlags;
4448}
4449
4451 bool ToBigInstrs) const {
4452 int Opcode = -1;
4453 if (ToBigInstrs) {
4454
4456
4458 } else
4460
4461
4462 if (Opcode >= 0)
4463 MII->setDesc(get(Opcode));
4464}
4465
4466
4467
4469 bool ToBigInstrs) const {
4470 for (auto &MB : MF)
4472 End = MB.instr_end();
4473 Instr != End; ++Instr)
4475}
4476
4477
4481 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4483 ++MII;
4484 }
4485}
4486
4488 using namespace HexagonII;
4489
4490 const uint64_t F = MI.getDesc().TSFlags;
4491 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4492 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4493 if (Size != 0)
4494 return Size;
4495
4496 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4498
4499
4501 switch (S) {
4503 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4504 default:
4506 }
4507}
4508
4509
4511 const uint64_t F = MI.getDesc().TSFlags;
4516
4517 if (isSigned)
4518 return -1U << (bits - 1);
4519 else
4520 return 0;
4521}
4522
4523
4525
4526
4527 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4528 if (NonExtOpcode >= 0)
4529 return NonExtOpcode;
4530
4531 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4532
4535 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4537 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4539 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4540
4541 default:
4542 return -1;
4543 }
4544 }
4545 return -1;
4546}
4547
4549 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4550 if (Cond.empty())
4551 return false;
4554 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4555 return false;
4556 }
4557 PredReg = Cond[1].getReg();
4558 PredRegPos = 1;
4559
4560 PredRegFlags = 0;
4561 if (Cond[1].isImplicit())
4565 return true;
4566}
4567
4569 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4570}
4571
4573 return Hexagon::getRegForm(MI.getOpcode());
4574}
4575
4576
4577
4578
4579
4581 if (MI.isDebugInstr() || MI.isPosition())
4582 return 0;
4583
4584 unsigned Size = MI.getDesc().getSize();
4586
4587
4589
4592
4593
4598
4599
4600 unsigned NumDefs = 0;
4601 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4602 ++NumDefs)
4603 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4604
4605 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4606
4607 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4609 }
4610
4611 return Size;
4612}
4613
4615 const uint64_t F = MI.getDesc().TSFlags;
4617}
4618
4621 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4622
4624}
4625
4626
4629}
4630
4633 assert(BundleHead->isBundle() && "Not a bundle header");
4635
4637}
4638
4639
4640
4643 "Instruction must be extendable");
4644
4647
4649 "Branch with unknown extendable field type");
4650
4652}
4653
4656 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4661 int TargetPos = MI.getNumOperands() - 1;
4662
4663
4664 while ((TargetPos > -1) && .getOperand(TargetPos).isMBB())
4665 --TargetPos;
4666 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4667 MI.getOperand(TargetPos).setMBB(NewTarget);
4670 }
4671 MI.setDesc(get(NewOpcode));
4672 return true;
4673}
4674
4676
4682
4683 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4684 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4690 }
4691
4692}
4693
4694
4695
4696
4700 return true;
4701}
4702
4703
4705 int PredRevOpcode = -1;
4707 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4708 else
4709 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4710 assert(PredRevOpcode > 0);
4711 return PredRevOpcode;
4712}
4713
4714
4716 const {
4717 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4718}
4719
4722 assert(MIB->isBundle());
4724 if (Operand.isImm())
4725 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4726 else
4728}
4729
4733 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4734}
4735
4736
4738 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4739}
4740
4742 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4743}
4744
4746 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4747}
4748
4750 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4751}
4752
4754 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4755}
4756
4758 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4759}
4760
4762 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4763}
4764
4766 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4767}
4768
4771
4775}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool mayAlias(MachineInstr &MIa, SmallVectorImpl< MachineInstr * > &MemInsns, AliasAnalysis *AA)
static bool isConstant(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static const Function * getParent(const Value *V)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static bool isSigned(unsigned int Opcode)
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))
const int Hexagon_MEMH_OFFSET_MAX
const int Hexagon_MEMB_OFFSET_MAX
const int Hexagon_MEMH_OFFSET_MIN
const int Hexagon_MEMD_OFFSET_MAX
static cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
const int Hexagon_MEMD_OFFSET_MIN
const int Hexagon_ADDI_OFFSET_MAX
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
const int Hexagon_MEMW_OFFSET_MIN
cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
const int Hexagon_ADDI_OFFSET_MIN
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))
static void parseOperands(const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
const int Hexagon_MEMB_OFFSET_MIN
static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
Calculate number of instructions excluding the debug instructions.
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI)
static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))
static bool isIntRegForSubInst(Register Reg)
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
#define HEXAGON_INSTR_SIZE
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t IntrinsicInst * II
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static StringRef getName(Value *V)
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
short getEquivalentHWInstr(const MachineInstr &MI) const
int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
short changeAddrMode_abs_io(short Opc) const
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
bool isVecALU(const MachineInstr &MI) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isJumpR(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isPredictedTaken(unsigned Opcode) const
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
unsigned getInvertedPredicatedOpcode(const int Opc) const
bool isPureSlot0(const MachineInstr &MI) const
bool doesNotReturn(const MachineInstr &CallMI) const
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool getPredReg(ArrayRef< MachineOperand > Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool isPredicatedNew(const MachineInstr &MI) const
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isVecAcc(const MachineInstr &MI) const
bool reversePredSense(MachineInstr &MI) const
unsigned getAddrMode(const MachineInstr &MI) const
MCInst getNop() const override
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
bool mayBeNewStore(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
bool isAddrModeWithOffset(const MachineInstr &MI) const
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool isBaseImmOffset(const MachineInstr &MI) const
bool isAbsoluteSet(const MachineInstr &MI) const
short changeAddrMode_io_pi(short Opc) const
short changeAddrMode_pi_io(short Opc) const
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool isLoopN(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isIndirectCall(const MachineInstr &MI) const
short changeAddrMode_ur_rr(short Opc) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
bool isConstExtended(const MachineInstr &MI) const
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
int getCondOpcode(int Opc, bool sense) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
bool isAccumulator(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool isNewValue(const MachineInstr &MI) const
Register createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
bool isDotCurInst(const MachineInstr &MI) const
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
bool isExtended(const MachineInstr &MI) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool isAsCheapAsAMove(const MachineInstr &MI) const override
int getMaxValue(const MachineInstr &MI) const
bool isPredicateLate(unsigned Opcode) const
short changeAddrMode_rr_ur(short Opc) const
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isNewValueInst(const MachineInstr &MI) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
int getNonDotCurOp(const MachineInstr &MI) const
bool isIndirectL4Return(const MachineInstr &MI) const
unsigned reversePrediction(unsigned Opcode) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
unsigned getMemAccessSize(const MachineInstr &MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
bool isComplex(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
int getDotNewOp(const MachineInstr &MI) const
void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const
bool isMemOp(const MachineInstr &MI) const
int getDotOldOp(const MachineInstr &MI) const
short getPseudoInstrPair(const MachineInstr &MI) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short getNonExtOpcode(const MachineInstr &MI) const
bool isTailCall(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool isDeallocRet(const MachineInstr &MI) const
unsigned getCExtOpNum(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isLateSourceInstr(const MachineInstr &MI) const
bool isDotNewInst(const MachineInstr &MI) const
void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const
bool isTC1(const MachineInstr &MI) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const
unsigned getSize(const MachineInstr &MI) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
short changeAddrMode_io_abs(short Opc) const
int getDotCurOp(const MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool isExpr(unsigned OpType) const
void genAllInsnTimingClasses(MachineFunction &MF) const
bool isTC2Early(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
bool hasEHLabel(const MachineBasicBlock *B) const
bool shouldSink(const MachineInstr &MI) const override
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_rr_io(short Opc) const
bool isHVXVec(const MachineInstr &MI) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
short changeAddrMode_io_rr(short Opc) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Emit instructions to copy a pair of physical registers.
bool mayBeCurLoad(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
bool isNewValueJump(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool isFloat(const MachineInstr &MI) const
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, LocationSize &AccessSize) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
uint64_t getType(const MachineInstr &MI) const
bool isEndLoopN(unsigned Opcode) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
bool isExtendable(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
HexagonInstrInfo(HexagonSubtarget &ST)
bool isPredicatedTrue(const MachineInstr &MI) const
bool isNewValueStore(const MachineInstr &MI) const
int getMinValue(const MachineInstr &MI) const
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTC2(const MachineInstr &MI) const
Register getStackRegister() const
Register getFrameRegister(const MachineFunction &MF) const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
bool usePredicatedCalls() const
const HexagonRegisterInfo * getRegisterInfo() const override
bool useNewValueStores() const
Itinerary data supplied by a subtarget to be used by a target.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * > > &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Represents a single loop in the control flow graph.
This class is intended to be used as a base class for asm properties and features specific to the tar...
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
StringRef getCommentString() const
const char * getSeparatorString() const
MCInstBuilder & addInst(const MCInst *Val)
Add a new MCInst operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Wrapper class representing physical registers. Should be passed by value.
instr_iterator instr_begin()
MachineInstrBundleIterator< const MachineInstr > const_iterator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
Instructions::iterator instr_iterator
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
instr_iterator instr_end()
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
instr_iterator getInstrIterator() const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
unsigned getNumOperands() const
Retuns the total number of operands.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
A description of a memory reference used in the backend.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
void addTargetFlag(unsigned F)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
size_t count(char C) const
Return the number of occurrences of C in the string.
Object returned by analyzeLoopForPipelining.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Primary interface to the complete machine description for the target machine.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSlot0Only(unsigned units)
unsigned const TypeCVI_LAST
unsigned const TypeCVI_FIRST
@ RestrictNoSlot1StoreMask
@ RestrictNoSlot1StorePos
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool is_TC1(unsigned SchedClass)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
auto reverse(ContainerTy &&C)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool is_TC2(unsigned SchedClass)
unsigned getUndefRegState(bool B)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
bool is_TC2early(unsigned SchedClass)
unsigned getKillRegState(bool B)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool is_TC4x(unsigned SchedClass)
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
These values represent a non-pipelined step in the execution of an instruction.
FuncUnits getUnits() const
Returns the choice of FUs.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.